[PATCH] D96589: [GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXT

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: dsanders, paquette.
Herald added subscribers: hiraditya, rovka.
foad requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

There's no need to call verifyVectorElementMatch since we already know
that the source and destination types are identical.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96589

Files:
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/test/MachineVerifier/test_g_assert_zext.mir
  llvm/test/MachineVerifier/test_g_sext_inreg.mir


Index: llvm/test/MachineVerifier/test_g_sext_inreg.mir
===================================================================
--- llvm/test/MachineVerifier/test_g_sext_inreg.mir
+++ llvm/test/MachineVerifier/test_g_sext_inreg.mir
@@ -36,11 +36,9 @@
 
    ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
    ; CHECK: instruction: %4:gpr(<2 x s32>) = G_SEXT_INREG
-   ; CHECK: *** Bad machine code: operand types must be all-vector or all-scalar ***
-   ; CHECK: instruction: %4:gpr(<2 x s32>) = G_SEXT_INREG
    %4(<2 x s32>) = G_SEXT_INREG %0, 8
 
-   ; CHECK: *** Bad machine code: operand types must preserve number of vector elements ***
+   ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
    ; CHECK: instruction: %5:gpr(<2 x s32>) = G_SEXT_INREG
    %5(<2 x s32>) = G_SEXT_INREG %1, 8
 
Index: llvm/test/MachineVerifier/test_g_assert_zext.mir
===================================================================
--- llvm/test/MachineVerifier/test_g_assert_zext.mir
+++ llvm/test/MachineVerifier/test_g_assert_zext.mir
@@ -19,11 +19,9 @@
 
    ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
    ; CHECK: instruction: %assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT
-   ; CHECK: *** Bad machine code: operand types must be all-vector or all-scalar ***
-   ; CHECK: instruction: %assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT
    %assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT %0, 8
 
-   ; CHECK: *** Bad machine code: operand types must preserve number of vector elements ***
+   ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
    ; CHECK: instruction: %assert_zext_4:_(<2 x s32>) = G_ASSERT_ZEXT
    %assert_zext_4:_(<2 x s32>) = G_ASSERT_ZEXT %1, 8
 
Index: llvm/lib/CodeGen/MachineVerifier.cpp
===================================================================
--- llvm/lib/CodeGen/MachineVerifier.cpp
+++ llvm/lib/CodeGen/MachineVerifier.cpp
@@ -949,9 +949,7 @@
 
     Register Dst = MI->getOperand(0).getReg();
     Register Src = MI->getOperand(1).getReg();
-    LLT DstTy = MRI->getType(Dst);
     LLT SrcTy = MRI->getType(Src);
-    verifyVectorElementMatch(DstTy, SrcTy, MI);
     int64_t Imm = MI->getOperand(2).getImm();
     if (Imm <= 0) {
       report("G_ASSERT_ZEXT size must be >= 1", MI);
@@ -1398,10 +1396,7 @@
       break;
     }
 
-    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
-    verifyVectorElementMatch(DstTy, SrcTy, MI);
-
     int64_t Imm = MI->getOperand(2).getImm();
     if (Imm <= 0)
       report("G_SEXT_INREG size must be >= 1", MI);


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D96589.323281.patch
Type: text/x-patch
Size: 2631 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210212/bf411fb6/attachment.bin>