[PATCH] D96518: [MIRLangRef] Document MachineOperand comments

[Sjoerd Meijer via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGcc4dcd48b84e: [MIRLangRef] Document MachineOperand comments (authored by SjoerdMeijer).

Changed prior to commit:
  https://reviews.llvm.org/D96518?vs=323038&id=323268#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96518/new/

https://reviews.llvm.org/D96518

Files:
  llvm/docs/MIRLangRef.rst


Index: llvm/docs/MIRLangRef.rst
===================================================================
--- llvm/docs/MIRLangRef.rst
+++ llvm/docs/MIRLangRef.rst
@@ -791,6 +791,24 @@
 .. TODO: Describe the syntax of the register live out machine operands.
 .. TODO: Describe the syntax of the machine memory operands.
 
+Comments
+^^^^^^^^
+
+Machine operands can have C/C++ style comments, which are annotations enclosed
+between ``/*`` and ``*/`` to improve readability of e.g. immediate operands.
+In the example below, ARM instructions EOR and BCC and immediate operands
+``14`` and ``0`` have been annotated with their condition codes (CC)
+definitions, i.e. the ``always`` and ``eq`` condition codes:
+
+.. code-block:: text
+
+  dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg
+  t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr
+
+As these annotations are comments, they are ignored by the MI parser.
+Comments can be added or customized by overriding InstrInfo's hook
+``createMIROperandComment()``.
+
 Debug-Info constructs
 ---------------------
 


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