[llvm] cc4dcd4 - [MIRLangRef] Document MachineOperand comments

[Sjoerd Meijer via llvm-commits]

Author: Sjoerd Meijer
Date: 2021-02-12T10:15:47Z
New Revision: cc4dcd48b84e9c2b66398b81d42d844629ed7b72

URL: https://github.com/llvm/llvm-project/commit/cc4dcd48b84e9c2b66398b81d42d844629ed7b72
DIFF: https://github.com/llvm/llvm-project/commit/cc4dcd48b84e9c2b66398b81d42d844629ed7b72.diff

LOG: [MIRLangRef] Document MachineOperand comments

Late follow-up of D74306 to document MachineOperand comments in
MIRLangRef.

Differential Revision: https://reviews.llvm.org/D96518

Added: 
    

Modified: 
    llvm/docs/MIRLangRef.rst

Removed: 
    


################################################################################
diff  --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst
index ff8029c5c646..ba6bdcbbed90 100644
--- a/llvm/docs/MIRLangRef.rst
+++ b/llvm/docs/MIRLangRef.rst
@@ -791,6 +791,24 @@ For an int eq predicate ``ICMP_EQ``, the syntax is:
 .. TODO: Describe the syntax of the register live out machine operands.
 .. TODO: Describe the syntax of the machine memory operands.
 
+Comments
+^^^^^^^^
+
+Machine operands can have C/C++ style comments, which are annotations enclosed
+between ``/*`` and ``*/`` to improve readability of e.g. immediate operands.
+In the example below, ARM instructions EOR and BCC and immediate operands
+``14`` and ``0`` have been annotated with their condition codes (CC)
+definitions, i.e. the ``always`` and ``eq`` condition codes:
+
+.. code-block:: text
+
+  dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg
+  t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr
+
+As these annotations are comments, they are ignored by the MI parser.
+Comments can be added or customized by overriding InstrInfo's hook
+``createMIROperandComment()``.
+
 Debug-Info constructs
 ---------------------