[PATCH] D93963: [GlobalISel][AMDGPU] Lower G_UMULO/G_SMULO

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:1894-1895
+  if (IsSigned) {
+    LeftOperand = MIRBuilder.buildSExtInReg(WideTy, LHS, SrcBitWidth);
+    RightOperand = MIRBuilder.buildSExtInReg(WideTy, RHS, SrcBitWidth);
+  } else {
----------------
Why is this using SExtInReg in the signed case, but ZExt in the other? SExtInReg doesn't widen the type


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93963/new/

https://reviews.llvm.org/D93963