[PATCH] D96552: [Vectorizers][TTI] remove option to bypass creation of vector reduction intrinsics

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: dmgreen, aemerson, nikic.
Herald added subscribers: kerbowa, pengfei, hiraditya, nhaehnle, jvesely, nemanjai, mcrosier.
spatel requested review of this revision.
Herald added a project: LLVM.

The vector reduction intrinsics started life as experimental ops, so backend support was lacking. As part of promoting them to 1st-class intrinsics, however, codegen support was added/improved:
D58015 <https://reviews.llvm.org/D58015>
D90247 <https://reviews.llvm.org/D90247>

So I think it is safe to now remove this complication from IR.

Note that we still have an IR-level codegen expansion pass for these as discussed in D95690 <https://reviews.llvm.org/D95690>. Removing that is another step in simplifying the logic. Also note that x86 was already unconditionally forming reductions in IR, so there should be no difference for x86.

I spot checked a couple of the tests here by running them though opt+llc and did not see any asm diffs.


https://reviews.llvm.org/D96552

Files:
  llvm/include/llvm/Analysis/TargetTransformInfo.h
  llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
  llvm/lib/Analysis/TargetTransformInfo.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
  llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
  llvm/lib/Target/ARM/ARMTargetTransformInfo.h
  llvm/lib/Target/X86/X86TargetTransformInfo.h
  llvm/lib/Transforms/Utils/LoopUtils.cpp
  llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
  llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
  llvm/test/Transforms/LoopVectorize/ARM/sphinx.ll
  llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll
  llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-vfabi-attr.ll
  llvm/test/Transforms/LoopVectorize/debugloc.ll
  llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
  llvm/test/Transforms/LoopVectorize/fix-reduction-dbg.ll
  llvm/test/Transforms/LoopVectorize/flags.ll
  llvm/test/Transforms/LoopVectorize/float-minmax-instruction-flag.ll
  llvm/test/Transforms/LoopVectorize/if-reduction.ll
  llvm/test/Transforms/LoopVectorize/induction.ll
  llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
  llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
  llvm/test/Transforms/LoopVectorize/loop-form.ll
  llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
  llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
  llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
  llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
  llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
  llvm/test/Transforms/LoopVectorize/reduction.ll
  llvm/test/Transforms/LoopVectorize/select-reduction.ll
  llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
  llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll

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