[PATCH] D96263: [RISCV] Support scalable-vector masked gather operations

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1778
+    // unsigned scaled indices it helps prevent overflow when scaling.
+    if (IndexVT.getVectorElementType().bitsLT(XLenVT)) {
+      IndexVT = IndexVT.changeVectorElementType(XLenVT);
----------------
Is it possible that IndexVT has 32-bit elements on a 64-bit target and that the IndexVT is already LMUL==8 such that this SIGN_EXTEND/ZERO_EXTEND would produce an illegal LMUL==16 type?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1788
+          !Subtarget.is64Bit() && IndexVT.getVectorElementType() == MVT::i64;
+      SDValue SplatScale = DAG.getConstant(Log2_32(N->getConstantOperandVal(5)),
+                                           DL, Subtarget.getXLenVT());
----------------
Assert that this is a power of 2. I'm not completely sure that's guaranteed, but maybe it is for the types we expect to see.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96263/new/

https://reviews.llvm.org/D96263