[llvm] ca052ad - Fix incorrect indentation in LangRef.rst

[Guillaume Chatelet via llvm-commits]

Author: Guillaume Chatelet
Date: 2021-02-11T20:34:19Z
New Revision: ca052adf07f0e5f453555053e0b0172e0b9f7309

URL: https://github.com/llvm/llvm-project/commit/ca052adf07f0e5f453555053e0b0172e0b9f7309
DIFF: https://github.com/llvm/llvm-project/commit/ca052adf07f0e5f453555053e0b0172e0b9f7309.diff

LOG: Fix incorrect indentation in LangRef.rst

Added: 
    

Modified: 
    llvm/docs/LangRef.rst

Removed: 
    


################################################################################
diff  --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index fdd9c14c5b7a..852b54897411 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -1988,7 +1988,7 @@ example:
     terminating loops without side-effects can be removed. If a `mustprogress`
     function does not satisfy this contract, the behavior is undefined.  This
     attribute does not apply transitively to callees, but does apply to call
-    sites within the function. Note that `willreturn` implies `mustprogress`. 
+    sites within the function. Note that `willreturn` implies `mustprogress`.
 
 Call Site Attributes
 ----------------------
@@ -4410,7 +4410,7 @@ PowerPC:
 - ``r``: A 32 or 64-bit integer register.
 - ``b``: A 32 or 64-bit integer register, excluding ``R0`` (that is:
   ``R1-R31``).
-- ``f``: A 32 or 64-bit float register (``F0-F31``), 
+- ``f``: A 32 or 64-bit float register (``F0-F31``),
 - ``v``: For ``4 x f32`` or ``4 x f64`` types, a 128-bit altivec vector
    register (``V0-V31``).
 
@@ -9652,9 +9652,9 @@ A ``cmpxchg`` instruction can also take an optional
 The instruction can take an optional ``align`` attribute.
 The alignment must be a power of two greater or equal to the size of the
 `<value>` type. If unspecified, the alignment is assumed to be equal to the
- size of the '<value>' type. Note that this default alignment assumption is
- 
diff erent from the alignment used for the load/store instructions when align
- isn't specified.
+size of the '<value>' type. Note that this default alignment assumption is
+
diff erent from the alignment used for the load/store instructions when align
+isn't specified.
 
 The pointer passed into cmpxchg must have alignment greater than or
 equal to the size in memory of the operand.
@@ -19674,7 +19674,7 @@ was only valid within a single iteration.
   entry:
     ; call void @llvm.experimental.noalias.scope.decl(metadata !2) ; Version 1: noalias decl outside loop
     br label %loop
-  
+
   loop:
     %a = phi i8* [ %a.base, %entry ], [ %a.inc, %loop ]
     %b = phi i8* [ %b.base, %entry ], [ %b.inc, %loop ]
@@ -19685,11 +19685,11 @@ was only valid within a single iteration.
     %b.inc = getelementptr inbounds i8, i8* %b, i64 1
     %cond = call i1 @cond()
     br i1 %cond, label %loop, label %exit
-  
+
   exit:
     ret void
   }
-  
+
   !0 = !{!0} ; domain
   !1 = !{!1, !0} ; scope
   !2 = !{!1} ; scope list