[PATCH] D90092: [AVR] Optimize 16-bit int shift

[Ayke via Phabricator via llvm-commits]

aykevl added a comment.

I found at least one code sample that is miscompiled.

Code:

  unsigned lsl(int a, int b, int c, int d, int e, int n) {
      return n << 4;
  }

Compiles to:

  lsl:                                    ; @lsl
          push    r14
          push    r15
          swap    r15
          swap    r14
          andi    r15, 240
          eor     r15, r14
          andi    r14, 240
          eor     r15, r14
          movw    r24, r14
          pop     r15
          pop     r14
          ret

However, `andi r15, 240` is not valid. According to the ISA specification, the register operand of `andi` must be in the range r16-r31.

Compiler Explorer: https://godbolt.org/z/qb9PWP


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90092/new/

https://reviews.llvm.org/D90092