[llvm] 6ef8473 - [InstCombine] add tests for disguised mul ops; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 11 10:40:46 PST 2021
Author: Sanjay Patel
Date: 2021-02-11T13:39:52-05:00
New Revision: 6ef84730157e6beb56c5fbd4b7541dd2f2be72f9
URL: https://github.com/llvm/llvm-project/commit/6ef84730157e6beb56c5fbd4b7541dd2f2be72f9
DIFF: https://github.com/llvm/llvm-project/commit/6ef84730157e6beb56c5fbd4b7541dd2f2be72f9.diff
LOG: [InstCombine] add tests for disguised mul ops; NFC
Added:
Modified:
llvm/test/Transforms/InstCombine/or-shifted-masks.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/or-shifted-masks.ll b/llvm/test/Transforms/InstCombine/or-shifted-masks.ll
index 2066f4a10f22..d67b4597a9df 100644
--- a/llvm/test/Transforms/InstCombine/or-shifted-masks.ll
+++ b/llvm/test/Transforms/InstCombine/or-shifted-masks.ll
@@ -1,10 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -instcombine < %s | FileCheck %s
define i32 @or_and_shifts1(i32 %x) {
; CHECK-LABEL: @or_and_shifts1(
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 3
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 8
-; CHECK-NEXT: [[TMP3:%.*]] = shl i32 %x, 5
+; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[X]], 5
; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 32
; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP4]]
; CHECK-NEXT: ret i32 [[TMP5]]
@@ -19,9 +20,9 @@ define i32 @or_and_shifts1(i32 %x) {
define i32 @or_and_shifts2(i32 %x) {
; CHECK-LABEL: @or_and_shifts2(
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 3
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 896
-; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 %x, 4
+; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[X]], 4
; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 7
; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP4]]
; CHECK-NEXT: ret i32 [[TMP5]]
@@ -36,9 +37,9 @@ define i32 @or_and_shifts2(i32 %x) {
define i32 @or_and_shift_shift_and(i32 %x) {
; CHECK-LABEL: @or_and_shift_shift_and(
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 3
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 56
-; CHECK-NEXT: [[TMP3:%.*]] = shl i32 %x, 2
+; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[X]], 2
; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 28
; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP4]]
; CHECK-NEXT: ret i32 [[TMP5]]
@@ -53,9 +54,9 @@ define i32 @or_and_shift_shift_and(i32 %x) {
define i32 @multiuse1(i32 %x) {
; CHECK-LABEL: @multiuse1(
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 6
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 6
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 384
-; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 %x, 1
+; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[X]], 1
; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 3
; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], [[TMP2]]
; CHECK-NEXT: ret i32 [[TMP5]]
@@ -74,14 +75,14 @@ define i32 @multiuse1(i32 %x) {
define i32 @multiuse2(i32 %x) {
; CHECK-LABEL: @multiuse2(
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 1
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 12
-; CHECK-NEXT: [[TMP3:%.*]] = shl i32 %x, 8
+; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[X]], 8
; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 24576
-; CHECK-NEXT: [[TMP5:%.*]] = shl i32 %x, 8
+; CHECK-NEXT: [[TMP5:%.*]] = shl i32 [[X]], 8
; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP5]], 7680
; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP4]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = shl i32 %x, 1
+; CHECK-NEXT: [[TMP8:%.*]] = shl i32 [[X]], 1
; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 240
; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP2]], [[TMP9]]
; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP7]], [[TMP10]]
@@ -106,13 +107,13 @@ define i32 @multiuse2(i32 %x) {
define i32 @multiuse3(i32 %x) {
; CHECK-LABEL: @multiuse3(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, 96
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 96
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 6
; CHECK-NEXT: [[TMP3:%.*]] = lshr exact i32 [[TMP1]], 1
-; CHECK-NEXT: [[TMP4:%.*]] = shl i32 %x, 6
+; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[X]], 6
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 1920
; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP2]], [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = lshr i32 %x, 1
+; CHECK-NEXT: [[TMP7:%.*]] = lshr i32 [[X]], 1
; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], 15
; CHECK-NEXT: [[TMP9:%.*]] = or i32 [[TMP3]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP6]]
@@ -133,23 +134,23 @@ define i32 @multiuse3(i32 %x) {
define i32 @multiuse4(i32 %x) local_unnamed_addr #0 {
; CHECK-LABEL: @multiuse4(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, 100663296
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 %x, -1
-; CHECK-NEXT: br i1 [[TMP2]], label %if, label %else
-; CHECK: {{.*}}if:{{.*}}
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 100663296
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[X]], -1
+; CHECK-NEXT: br i1 [[TMP2]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK: if:
; CHECK-NEXT: [[TMP3:%.*]] = lshr exact i32 [[TMP1]], 22
-; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 %x, 22
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[X]], 22
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 480
; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[TMP3]]
-; CHECK-NEXT: br label %end
-; CHECK: {{.*}}else:{{.*}}
+; CHECK-NEXT: br label [[END:%.*]]
+; CHECK: else:
; CHECK-NEXT: [[TMP7:%.*]] = lshr exact i32 [[TMP1]], 17
-; CHECK-NEXT: [[TMP8:%.*]] = lshr i32 %x, 17
+; CHECK-NEXT: [[TMP8:%.*]] = lshr i32 [[X]], 17
; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 15360
; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP7]]
-; CHECK-NEXT: br label %end
-; CHECK: {{.*}}end{{.*}}
-; CHECK-NEXT: [[TMP11:%.*]] = phi i32 [ [[TMP6]], %if ], [ [[TMP10]], %else ]
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[TMP11:%.*]] = phi i32 [ [[TMP6]], [[IF]] ], [ [[TMP10]], [[ELSE]] ]
; CHECK-NEXT: ret i32 [[TMP11]]
;
%1 = and i32 %x, 100663296
@@ -177,23 +178,23 @@ end:
define i32 @multiuse5(i32 %x) local_unnamed_addr #0 {
; CHECK-LABEL: @multiuse5(
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 5
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 %x, -1
-; CHECK-NEXT: br i1 [[TMP2]], label %if, label %else
-; CHECK: {{.*}}if:{{.*}}
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 5
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[X]], -1
+; CHECK-NEXT: br i1 [[TMP2]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK: if:
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP1]], 21760
-; CHECK-NEXT: [[TMP4:%.*]] = shl i32 %x, 5
+; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[X]], 5
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 43520
; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[TMP3]]
-; CHECK-NEXT: br label %end
-; CHECK: {{.*}}else:{{.*}}
+; CHECK-NEXT: br label [[END:%.*]]
+; CHECK: else:
; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP1]], 5570560
-; CHECK-NEXT: [[TMP8:%.*]] = shl i32 %x, 5
+; CHECK-NEXT: [[TMP8:%.*]] = shl i32 [[X]], 5
; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 11141120
; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP7]]
-; CHECK-NEXT: br label %end
-; CHECK: {{.*}}end{{.*}}
-; CHECK-NEXT: [[TMP11:%.*]] = phi i32 [ [[TMP6]], %if ], [ [[TMP10]], %else ]
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: [[TMP11:%.*]] = phi i32 [ [[TMP6]], [[IF]] ], [ [[TMP10]], [[ELSE]] ]
; CHECK-NEXT: ret i32 [[TMP11]]
;
%1 = shl i32 %x, 5
@@ -219,3 +220,88 @@ end:
ret i32 %11
}
+define i32 @shl_mask(i32 %x) {
+; CHECK-LABEL: @shl_mask(
+; CHECK-NEXT: [[Z:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT: [[S:%.*]] = shl nuw nsw i32 [[Z]], 8
+; CHECK-NEXT: [[R:%.*]] = or i32 [[Z]], [[S]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %z = and i32 %x, 255
+ %s = shl i32 %z, 8
+ %r = or i32 %z, %s
+ ret i32 %r
+}
+
+define i32 @shl_mask_wrong_shl_const(i32 %x) {
+; CHECK-LABEL: @shl_mask_wrong_shl_const(
+; CHECK-NEXT: [[Z:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT: [[S:%.*]] = shl nuw nsw i32 [[Z]], 7
+; CHECK-NEXT: [[R:%.*]] = or i32 [[Z]], [[S]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %z = and i32 %x, 255
+ %s = shl i32 %z, 7
+ %r = or i32 %z, %s
+ ret i32 %r
+}
+
+define i37 @shl_mask_weird_type(i37 %x) {
+; CHECK-LABEL: @shl_mask_weird_type(
+; CHECK-NEXT: [[Z:%.*]] = and i37 [[X:%.*]], 255
+; CHECK-NEXT: [[S:%.*]] = shl nuw nsw i37 [[Z]], 8
+; CHECK-NEXT: [[R:%.*]] = or i37 [[Z]], [[S]]
+; CHECK-NEXT: ret i37 [[R]]
+;
+ %z = and i37 %x, 255
+ %s = shl i37 %z, 8
+ %r = or i37 %z, %s
+ ret i37 %r
+}
+
+define i32 @shl_mask_extra_use(i32 %x, i32* %p) {
+; CHECK-LABEL: @shl_mask_extra_use(
+; CHECK-NEXT: [[Z:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT: [[S:%.*]] = shl nuw nsw i32 [[Z]], 8
+; CHECK-NEXT: store i32 [[S]], i32* [[P:%.*]], align 4
+; CHECK-NEXT: [[R:%.*]] = or i32 [[Z]], [[S]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %z = and i32 %x, 255
+ %s = shl i32 %z, 8
+ store i32 %s, i32* %p
+ %r = or i32 %z, %s
+ ret i32 %r
+}
+
+; This could be "Z * 65793".
+
+define i32 @shl_mul_mask(i32 %x) {
+; CHECK-LABEL: @shl_mul_mask(
+; CHECK-NEXT: [[Z:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT: [[M:%.*]] = mul nuw nsw i32 [[Z]], 65537
+; CHECK-NEXT: [[S:%.*]] = shl nuw nsw i32 [[Z]], 8
+; CHECK-NEXT: [[R:%.*]] = or i32 [[M]], [[S]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %z = and i32 %x, 255
+ %m = mul i32 %z, 65537
+ %s = shl i32 %z, 8
+ %r = or i32 %m, %s
+ ret i32 %r
+}
+
+define i32 @shl_mul_mask_wrong_mul_const(i32 %x) {
+; CHECK-LABEL: @shl_mul_mask_wrong_mul_const(
+; CHECK-NEXT: [[Z:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT: [[M:%.*]] = mul nuw nsw i32 [[Z]], 65535
+; CHECK-NEXT: [[S:%.*]] = shl nuw nsw i32 [[Z]], 8
+; CHECK-NEXT: [[R:%.*]] = or i32 [[M]], [[S]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %z = and i32 %x, 255
+ %m = mul i32 %z, 65535
+ %s = shl i32 %z, 8
+ %r = or i32 %m, %s
+ ret i32 %r
+}
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