[PATCH] D96421: [AMDGPU] Better selection of base offset when merging DS reads/writes

[Jay Foad via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG23db2d363fd3: [AMDGPU] Better selection of base offset when merging DS reads/writes (authored by foad).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96421/new/

https://reviews.llvm.org/D96421

Files:
  llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
  llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
  llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir

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