[PATCH] D96424: [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 11 08:36:57 PST 2021
dmgreen added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h:31-32
bool ZeroData) const override;
- bool generateFMAsInMachineCombiner(CodeGenOpt::Level OptLevel) const override;
+ bool generateFMAsInMachineCombiner(SelectionDAG &DAG,
+ CodeGenOpt::Level OptLevel) const override;
};
----------------
dmgreen wrote:
> Could we just make it so that AArch64Subtarget->TSInfo is passed the subtarget directly on construction?
Alternatively, I'm not sure why this function is here in AArch64SelectionDAGInfo and could possibly just be moved to AArch64TargetLowering?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D96424/new/
https://reviews.llvm.org/D96424
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