[PATCH] D96210: [TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 322472.
craig.topper added a comment.

Use getShiftAmountConstant


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96210/new/

https://reviews.llvm.org/D96210

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/BPF/BPFISelLowering.h
  llvm/test/CodeGen/AArch64/srem-seteq.ll
  llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
  llvm/test/CodeGen/AArch64/urem-seteq.ll
  llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
  llvm/test/CodeGen/RISCV/div.ll
  llvm/test/CodeGen/RISCV/srem-lkk.ll
  llvm/test/CodeGen/RISCV/urem-lkk.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D96210.322472.patch
Type: text/x-patch
Size: 26948 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210209/d67694c9/attachment-0001.bin>