[PATCH] D96506: [AVR] Optimize 16-bit shifts

[Ben Shi via Phabricator via llvm-commits]

benshi001 added a comment.

For `int >> 9`, the following instructions are genreated

  mov r24, r25
  clr r25
  lsr r25
  ror r24

However the `ror` is unecessary, it can be simpilfied to

  mov r24, r25
  clr r25
  lsr r24


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https://reviews.llvm.org/D96506