[PATCH] D96421: [AMDGPU] Better selection of base offset when merging DS reads/writes

[Jay Foad via Phabricator via llvm-commits]

foad updated this revision to Diff 323004.
foad added a comment.

Split out mostAlignedValueInRange.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96421/new/

https://reviews.llvm.org/D96421

Files:
  llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
  llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
  llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D96421.323004.patch
Type: text/x-patch
Size: 18871 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210211/4c68a2d4/attachment-0001.bin>