[PATCH] D96424: [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD

[Bradley Smith via Phabricator via llvm-commits]

bsmith added a comment.

In D96424#2556165 <https://reviews.llvm.org/D96424#2556165>, @dmgreen wrote:

> Hello. Would the machine combiner method not be better, if it can reduce critical path length?

In principal it perhaps would yes, however I'm not sure by itself it is up to the task. The main issue here is the fact that there are different instructions available depending on whether you have a predicate or not, (notably the combined instructions (FMLA etc) have only predicated forms). As such, ISelLowering lowers nodes (e.g. FADD + FMUL) to predicated forms to allow instruction selection to either select these predicated combined instructions (FMLA) or to select in such a way that the predicate is removed again if it could not combine instructions.

If this instruction combining was deferred to the machine combiner then either it would have to learn how to add PTRUES in to allow use of predicated forms, or ISelLowering would keep lowering to predicated forms and in the case of no combining happening a later post machine combiner pass would have to remove PTRUES that were no longer needed and revert instructions to unpredicated forms. Essentially doing it this way allows for a lot of this complexity to be taken care of by lowering and instruction selection.

Perhaps in the future this is something that could be addressed, but for now I think this is a reasonable approach.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96424/new/

https://reviews.llvm.org/D96424