[llvm] 6efcc2f - [Test] Add negative tests where usub optimization should not apply

Max Kazantsev via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 10 21:00:02 PST 2021


Author: Max Kazantsev
Date: 2021-02-11T11:59:44+07:00
New Revision: 6efcc2fd3f138160a710f3c152ee1c54c2e50420

URL: https://github.com/llvm/llvm-project/commit/6efcc2fd3f138160a710f3c152ee1c54c2e50420
DIFF: https://github.com/llvm/llvm-project/commit/6efcc2fd3f138160a710f3c152ee1c54c2e50420.diff

LOG: [Test] Add negative tests where usub optimization should not apply

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/usub_inc_iv.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/usub_inc_iv.ll b/llvm/test/CodeGen/X86/usub_inc_iv.ll
index 4cc0fedab3a3..7bf8b5e8b147 100644
--- a/llvm/test/CodeGen/X86/usub_inc_iv.ll
+++ b/llvm/test/CodeGen/X86/usub_inc_iv.ll
@@ -96,7 +96,6 @@ failure:                                          ; preds = %backedge
   unreachable
 }
 
-
 ; TODO: We can use trick with usub here.
 define i32 @test_02(i32* %p, i64 %len, i32 %x) {
 ; CHECK-LABEL: @test_02(
@@ -143,3 +142,118 @@ exit:                                             ; preds = %loop
 failure:                                          ; preds = %backedge
   unreachable
 }
+
+declare i1 @use(i64 %x)
+declare i1 @some_cond()
+
+; Make sure we do not move the increment below the point where it is used.
+define i32 @test_03_neg(i32* %p, i64 %len, i32 %x) {
+; CHECK-LABEL: @test_03_neg(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[IV_NEXT]] = add i64 [[IV]], -1
+; CHECK-NEXT:    [[COND_0:%.*]] = call i1 @use(i64 [[IV_NEXT]])
+; CHECK-NEXT:    br i1 [[COND_0]], label [[MIDDLE:%.*]], label [[FAILURE:%.*]]
+; CHECK:       middle:
+; CHECK-NEXT:    [[COND_1:%.*]] = icmp eq i64 [[IV]], 0
+; CHECK-NEXT:    br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]
+; CHECK:       backedge:
+; CHECK-NEXT:    [[SUNKADDR:%.*]] = mul i64 [[IV]], 4
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to i8*
+; CHECK-NEXT:    [[SUNKADDR1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 [[SUNKADDR]]
+; CHECK-NEXT:    [[SUNKADDR2:%.*]] = getelementptr i8, i8* [[SUNKADDR1]], i64 -4
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[SUNKADDR2]] to i32*
+; CHECK-NEXT:    [[LOADED:%.*]] = load atomic i32, i32* [[TMP1]] unordered, align 4
+; CHECK-NEXT:    [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]
+; CHECK-NEXT:    br i1 [[COND_2]], label [[FAILURE]], label [[LOOP]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i32 -1
+; CHECK:       failure:
+; CHECK-NEXT:    unreachable
+;
+entry:
+  %scevgep = getelementptr i32, i32* %p, i64 -1
+  br label %loop
+
+loop:                                             ; preds = %backedge, %entry
+  %iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
+  %iv.next = add i64 %iv, -1
+  %cond_0 = call i1 @use(i64 %iv.next)
+  br i1 %cond_0, label %middle, label %failure
+
+middle:
+  %cond_1 = icmp eq i64 %iv, 0
+  br i1 %cond_1, label %exit, label %backedge
+
+backedge:                                         ; preds = %loop
+  %scevgep1 = getelementptr i32, i32* %scevgep, i64 %iv
+  %loaded = load atomic i32, i32* %scevgep1 unordered, align 4
+  %cond_2 = icmp eq i32 %loaded, %x
+  br i1 %cond_2, label %failure, label %loop
+
+exit:                                             ; preds = %loop
+  ret i32 -1
+
+failure:                                          ; preds = %backedge
+  unreachable
+}
+
+define i32 @test_04_neg(i32* %p, i64 %len, i32 %x) {
+; CHECK-LABEL: @test_04_neg(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]
+; CHECK-NEXT:    br label [[INNER:%.*]]
+; CHECK:       inner:
+; CHECK-NEXT:    [[COND_1:%.*]] = icmp eq i64 [[IV]], 0
+; CHECK-NEXT:    br i1 [[COND_1]], label [[INNER_BACKEDGE:%.*]], label [[EXIT:%.*]]
+; CHECK:       inner_backedge:
+; CHECK-NEXT:    [[COND_INNER:%.*]] = call i1 @some_cond()
+; CHECK-NEXT:    br i1 [[COND_INNER]], label [[INNER]], label [[BACKEDGE]]
+; CHECK:       backedge:
+; CHECK-NEXT:    [[SUNKADDR:%.*]] = mul i64 [[IV]], 4
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to i8*
+; CHECK-NEXT:    [[SUNKADDR1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 [[SUNKADDR]]
+; CHECK-NEXT:    [[SUNKADDR2:%.*]] = getelementptr i8, i8* [[SUNKADDR1]], i64 -4
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[SUNKADDR2]] to i32*
+; CHECK-NEXT:    [[LOADED:%.*]] = load atomic i32, i32* [[TMP1]] unordered, align 4
+; CHECK-NEXT:    [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]
+; CHECK-NEXT:    [[IV_NEXT]] = add i64 [[IV]], -1
+; CHECK-NEXT:    br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i32 -1
+; CHECK:       failure:
+; CHECK-NEXT:    unreachable
+;
+entry:
+  %scevgep = getelementptr i32, i32* %p, i64 -1
+  br label %loop
+
+loop:
+  %iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
+  br label %inner
+
+inner:
+  %cond_1 = icmp eq i64 %iv, 0
+  br i1 %cond_1, label %inner_backedge, label %exit
+
+inner_backedge:
+  %cond_inner = call i1 @some_cond()
+  br i1 %cond_inner, label %inner, label %backedge
+
+backedge:
+  %scevgep1 = getelementptr i32, i32* %scevgep, i64 %iv
+  %loaded = load atomic i32, i32* %scevgep1 unordered, align 4
+  %cond_2 = icmp eq i32 %loaded, %x
+  %iv.next = add i64 %iv, -1
+  br i1 %cond_2, label %failure, label %loop
+
+exit:
+  ret i32 -1
+
+failure:
+  unreachable
+}


        


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