[llvm] 5f7a4d8 - [AArch64][GlobalISel] Perform load/store extended reg folding with optsize

[Jessica Paquette via llvm-commits]

Author: Jessica Paquette
Date: 2021-02-10T14:42:25-08:00
New Revision: 5f7a4d8d05896c2d54a3d67cc3fd1fd81a84b2df

URL: https://github.com/llvm/llvm-project/commit/5f7a4d8d05896c2d54a3d67cc3fd1fd81a84b2df
DIFF: https://github.com/llvm/llvm-project/commit/5f7a4d8d05896c2d54a3d67cc3fd1fd81a84b2df.diff

LOG: [AArch64][GlobalISel] Perform load/store extended reg folding with optsize

GlobalISel was only doing this with minsize. SDAG does this with optsize.

(See: `SelectionDAG::shouldOptForSize()`)

This is a 0.3% code size improvement for CTMark at -Os.

(Best: 1.1% improvements on lencod + pairlocalalign)

Differential Revision: https://reviews.llvm.org/D96451

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index decf71fa8af0..bf44fa73e53d 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -5219,7 +5219,7 @@ bool AArch64InstructionSelector::isWorthFoldingIntoExtendedReg(
   // Always fold if there is one use, or if we're optimizing for size.
   Register DefReg = MI.getOperand(0).getReg();
   if (MRI.hasOneNonDBGUse(DefReg) ||
-      MI.getParent()->getParent()->getFunction().hasMinSize())
+      MI.getParent()->getParent()->getFunction().hasOptSize())
     return true;
 
   // It's better to avoid folding and recomputing shifts when we don't have a

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
index 8b8d66541469..91b681b9b9bb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
@@ -23,7 +23,7 @@
   define void @ldrhrox(i64* %addr) { ret void }
   define void @ldbbrox(i64* %addr) { ret void }
   define void @ldrqrox(i64* %addr) { ret void }
-  attributes #0 = { optsize minsize }
+  attributes #0 = { optsize }
   attributes #1 = { "target-features"="+lsl-fast" }
 ...