[PATCH] D91629: [PowerPC] Handle FP physical register in inline asm constraint.

[Zarko Todorovski via Phabricator via llvm-commits]

ZarkoCA accepted this revision.
ZarkoCA added a comment.
This revision is now accepted and ready to land.

LGTM, only some question about a comment.



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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15610
+    // For float registers, we can't defer to the base class as it will match
+    // the SPILLTOVSX class.
+    if (Constraint.size() > 3 && Constraint[1] == 'f') {
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I think this should be `SPILLTOVSRRC` instead of `SPILLTOVSX`


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  https://reviews.llvm.org/D91629/new/

https://reviews.llvm.org/D91629