[PATCH] D96443: [RISCV] Add support for integer fixed vector setcc and storing a mask vector.

[Craig Topper via Phabricator via llvm-commits]

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I believe I've covered all orderings of splat operands here. Better
canonicalization in lowering might help reduce this. I did not handle
the immediate adjustments needed for set(u)gt/set(u)lt.

Testing here is limited to byte types because the scalable vector
type used for masks for the store is calculated assuming 8 byte
elements. But for the setcc its based on the element count of the
container type for the setcc input. So they don't agree. We'll need
to enhanced D96352 <https://reviews.llvm.org/D96352> to handle this I think.

Once we have mask sign/zero extend support we can probably also avoid
these mask stores in the test. I may have made a bad patch order
decision here.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96443

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll

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