[PATCH] D96424: [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD

[Bradley Smith via Phabricator via llvm-commits]

bsmith created this revision.
bsmith added reviewers: peterwaller-arm, paulwalker-arm, joechrisellis.
Herald added subscribers: ecnelises, psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
bsmith requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Add tablegen patterns for a variety of FP multiply type instructions.

Adjust generateFMAsInMachineCombiner to return false if SVE is present
in order to combine fmul+fadd into fma. Also add new pseudo instructions
so as to select the most appropriate of FMLA/FMAD depending on register
allocation.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96424

Files:
  llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
  llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
  llvm/test/CodeGen/AArch64/sve-fma-dagcombine.ll
  llvm/test/CodeGen/AArch64/sve-fp-combine.ll
  llvm/test/CodeGen/AArch64/sve-fp.ll

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