[llvm] 2114b45 - [AMDGPU] Fix comments in SILoadStoreOptimizer::offsetsCanBeCombined

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-02-10T14:49:33Z
New Revision: 2114b458b0cda7d2be082181fc6d0fcebdbdd9b9

URL: https://github.com/llvm/llvm-project/commit/2114b458b0cda7d2be082181fc6d0fcebdbdd9b9
DIFF: https://github.com/llvm/llvm-project/commit/2114b458b0cda7d2be082181fc6d0fcebdbdd9b9.diff

LOG: [AMDGPU] Fix comments in SILoadStoreOptimizer::offsetsCanBeCombined

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index b39420f3c7db..6da3f6f591e1 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -769,7 +769,7 @@ bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI,
   CI.UseST64 = false;
   CI.BaseOff = 0;
 
-  // Handle DS instructions.
+  // Handle all non-DS instructions.
   if ((CI.InstClass != DS_READ) && (CI.InstClass != DS_WRITE)) {
     return (EltOffset0 + CI.Width == EltOffset1 ||
             EltOffset1 + Paired.Width == EltOffset0) &&
@@ -777,7 +777,6 @@ bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI,
            (CI.InstClass == S_BUFFER_LOAD_IMM || CI.SLC == Paired.SLC);
   }
 
-  // Handle SMEM and VMEM instructions.
   // If the offset in elements doesn't fit in 8-bits, we might be able to use
   // the stride 64 versions.
   if ((EltOffset0 % 64 == 0) && (EltOffset1 % 64) == 0 &&