[PATCH] D96405: [DAGCombiner] Improve reduceBuildVecToShuffle Performance

[Michael Marjieh via Phabricator via llvm-commits]

mmarjieh created this revision.
Herald added subscribers: ecnelises, pengfei, dmgreen, hiraditya, nemanjai.
mmarjieh requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This patche modifies the implementation of reduceBuildVecToShuffle to
try reducing the number of generated vector_shuffle nodes.
For example:

Instead of generating the following nodes:
t0: v8i32 = vector_shuffle<0,5,u,u,u,u,u,u> t3, undef
t1: v8i32 = vector_shuffle<u,u,0,8,u,u,u,u> t4, t5
t2: v8i32 = vector_shuffle<0,1,10,11> t0, t1

Generate this:
t1: v8i32 = vector_shuffle<u,u,0,8,u,u,u,u> t4, t5
t2: v8i32 = vector_shuffle<0,5,10,11> t3, t1


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96405

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/ARM/fp16-insert-extract.ll
  llvm/test/CodeGen/PowerPC/pr27078.ll
  llvm/test/CodeGen/PowerPC/vec-itofp.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
  llvm/test/CodeGen/Thumb2/mve-shuffle.ll
  llvm/test/CodeGen/Thumb2/mve-vld3.ll
  llvm/test/CodeGen/Thumb2/mve-vst3.ll
  llvm/test/CodeGen/Thumb2/mve-vst4.ll
  llvm/test/CodeGen/X86/insertelement-duplicates.ll
  llvm/test/CodeGen/X86/oddshuffles.ll
  llvm/test/CodeGen/X86/pr34592.ll
  llvm/test/CodeGen/X86/split-extend-vector-inreg.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D96405.322640.patch
Type: text/x-patch
Size: 134831 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210210/b90b7bb3/attachment-0001.bin>