[llvm] 7e75f6f - [SelectionDAG] Use range-based for loops (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 9 22:14:53 PST 2021
Author: Kazu Hirata
Date: 2021-02-09T22:14:30-08:00
New Revision: 7e75f6fc1d55d96c2abbde10f4aed619bb322956
URL: https://github.com/llvm/llvm-project/commit/7e75f6fc1d55d96c2abbde10f4aed619bb322956
DIFF: https://github.com/llvm/llvm-project/commit/7e75f6fc1d55d96c2abbde10f4aed619bb322956.diff
LOG: [SelectionDAG] Use range-based for loops (NFC)
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 762f58427649..64f92734196f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -15975,12 +15975,9 @@ bool DAGCombiner::SliceUpLoad(SDNode *N) {
// Prepare the argument for the new token factor for all the slices.
SmallVector<SDValue, 8> ArgChains;
- for (SmallVectorImpl<LoadedSlice>::const_iterator
- LSIt = LoadedSlices.begin(),
- LSItEnd = LoadedSlices.end();
- LSIt != LSItEnd; ++LSIt) {
- SDValue SliceInst = LSIt->loadSlice();
- CombineTo(LSIt->Inst, SliceInst, true);
+ for (const LoadedSlice &LS : LoadedSlices) {
+ SDValue SliceInst = LS.loadSlice();
+ CombineTo(LS.Inst, SliceInst, true);
if (SliceInst.getOpcode() != ISD::LOAD)
SliceInst = SliceInst.getOperand(0);
assert(SliceInst->getOpcode() == ISD::LOAD &&
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
index a59f03854775..05a974af3b55 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
@@ -182,9 +182,8 @@ void DAGTypeLegalizer::PerformExpensiveChecks() {
// Checked that NewNodes are only used by other NewNodes.
for (unsigned i = 0, e = NewNodes.size(); i != e; ++i) {
SDNode *N = NewNodes[i];
- for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
- UI != UE; ++UI)
- assert(UI->getNodeId() == NewNode && "NewNode used by non-NewNode!");
+ for (SDNode *U : N->uses())
+ assert(U->getNodeId() == NewNode && "NewNode used by non-NewNode!");
}
#endif
}
@@ -396,9 +395,7 @@ bool DAGTypeLegalizer::run() {
assert(N->getNodeId() == ReadyToProcess && "Node ID recalculated?");
N->setNodeId(Processed);
- for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
- UI != E; ++UI) {
- SDNode *User = *UI;
+ for (SDNode *User : N->uses()) {
int NodeId = User->getNodeId();
// This node has two options: it can either be a new node or its Node ID
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index debfdda90e1e..277a32283b0d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -790,20 +790,21 @@ ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
void ScheduleDAGSDNodes::
EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, Register> &VRBaseMap,
MachineBasicBlock::iterator InsertPos) {
- for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
- I != E; ++I) {
- if (I->isCtrl()) continue; // ignore chain preds
- if (I->getSUnit()->CopyDstRC) {
+ for (const SDep &Pred : SU->Preds) {
+ if (Pred.isCtrl())
+ continue; // ignore chain preds
+ if (Pred.getSUnit()->CopyDstRC) {
// Copy to physical register.
- DenseMap<SUnit*, Register>::iterator VRI = VRBaseMap.find(I->getSUnit());
+ DenseMap<SUnit *, Register>::iterator VRI =
+ VRBaseMap.find(Pred.getSUnit());
assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
// Find the destination physical register.
Register Reg;
- for (SUnit::const_succ_iterator II = SU->Succs.begin(),
- EE = SU->Succs.end(); II != EE; ++II) {
- if (II->isCtrl()) continue; // ignore chain preds
- if (II->getReg()) {
- Reg = II->getReg();
+ for (const SDep &Succ : SU->Succs) {
+ if (Succ.isCtrl())
+ continue; // ignore chain preds
+ if (Succ.getReg()) {
+ Reg = Succ.getReg();
break;
}
}
@@ -811,13 +812,13 @@ EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, Register> &VRBaseMap,
.addReg(VRI->second);
} else {
// Copy from physical register.
- assert(I->getReg() && "Unknown physical register!");
+ assert(Pred.getReg() && "Unknown physical register!");
Register VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
(void)isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
- .addReg(I->getReg());
+ .addReg(Pred.getReg());
}
break;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
index e7bac73678a7..540a6e3efbe1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
@@ -136,12 +136,11 @@ void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) {
void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) {
// Top down: release successors.
- for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
- I != E; ++I) {
- assert(!I->isAssignedRegDep() &&
+ for (SDep &Succ : SU->Succs) {
+ assert(!Succ.isAssignedRegDep() &&
"The list-td scheduler doesn't yet support physreg dependencies!");
- releaseSucc(SU, *I);
+ releaseSucc(SU, Succ);
}
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index f01b5b3092c6..cf1eee48e6b7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -932,12 +932,12 @@ static void VerifySDNode(SDNode *N) {
assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
"Wrong number of operands!");
EVT EltVT = N->getValueType(0).getVectorElementType();
- for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) {
- assert((I->getValueType() == EltVT ||
- (EltVT.isInteger() && I->getValueType().isInteger() &&
- EltVT.bitsLE(I->getValueType()))) &&
- "Wrong operand type!");
- assert(I->getValueType() == N->getOperand(0).getValueType() &&
+ for (const SDUse &Op : N->ops()) {
+ assert((Op.getValueType() == EltVT ||
+ (EltVT.isInteger() && Op.getValueType().isInteger() &&
+ EltVT.bitsLE(Op.getValueType()))) &&
+ "Wrong operand type!");
+ assert(Op.getValueType() == N->getOperand(0).getValueType() &&
"Operands must all have the same type");
}
break;
@@ -6844,8 +6844,8 @@ SDValue SelectionDAG::getMergeValues(ArrayRef<SDValue> Ops, const SDLoc &dl) {
SmallVector<EVT, 4> VTs;
VTs.reserve(Ops.size());
- for (unsigned i = 0; i < Ops.size(); ++i)
- VTs.push_back(Ops[i].getValueType());
+ for (const SDValue &Op : Ops)
+ VTs.push_back(Op.getValueType());
return getNode(ISD::MERGE_VALUES, dl, getVTList(VTs), Ops);
}
@@ -8970,9 +8970,7 @@ unsigned SelectionDAG::AssignTopologicalOrder() {
checkForCycles(N, this);
// N is in sorted position, so all its uses have one less operand
// that needs to be sorted.
- for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
- UI != UE; ++UI) {
- SDNode *P = *UI;
+ for (SDNode *P : N->uses()) {
unsigned Degree = P->getNodeId();
assert(Degree != 0 && "Invalid node degree");
--Degree;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 5c94a83f719c..4fbfe45283ea 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -6664,9 +6664,8 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
SmallVector<const Value *, 4> Allocas;
getUnderlyingObjects(ObjectPtr, Allocas);
- for (SmallVectorImpl<const Value*>::iterator Object = Allocas.begin(),
- E = Allocas.end(); Object != E; ++Object) {
- const AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
+ for (const Value *Alloca : Allocas) {
+ const AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(Alloca);
// Could not find an Alloca.
if (!LifetimeObject)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 7bae5048fc0e..c58452c2235d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1419,9 +1419,8 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
for (const BasicBlock *LLVMBB : RPOT) {
if (OptLevel != CodeGenOpt::None) {
bool AllPredsVisited = true;
- for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
- PI != PE; ++PI) {
- if (!FuncInfo->VisitedBBs.count(*PI)) {
+ for (const BasicBlock *Pred : predecessors(LLVMBB)) {
+ if (!FuncInfo->VisitedBBs.count(Pred)) {
AllPredsVisited = false;
break;
}
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