[PATCH] D96365: [RISCV] Add support for matching .vx and .vi forms of binary instructions for fixed vectors.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 322496.
craig.topper added a comment.

Remove unused AVL operand from new tablegen classes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96365/new/

https://reviews.llvm.org/D96365

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

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