[llvm] 0e85d63 - [AArch64][GlobalISel] Allow vector load legalization into 128-bit-wide types
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 9 13:43:12 PST 2021
Author: Jessica Paquette
Date: 2021-02-09T13:35:59-08:00
New Revision: 0e85d634865308854cba83897325cfa9c3994e33
URL: https://github.com/llvm/llvm-project/commit/0e85d634865308854cba83897325cfa9c3994e33
DIFF: https://github.com/llvm/llvm-project/commit/0e85d634865308854cba83897325cfa9c3994e33.diff
LOG: [AArch64][GlobalISel] Allow vector load legalization into 128-bit-wide types
Similar to 3d25fdc5c21f174d38ac78dd01ccaf6eec655bc0
This fixes bad codegen in cases like so:
https://godbolt.org/z/hePhz1
Differential Revision: https://reviews.llvm.org/D96296
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 6069b1051da9..09de46a6f18f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -293,8 +293,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
return Query.Types[0].getSizeInBits() != Query.MMODescrs[0].SizeInBits;
})
.widenScalarToNextPow2(0)
- .clampMaxNumElements(0, s32, 2)
- .clampMaxNumElements(0, s64, 1)
+ .clampMaxNumElements(0, s8, 16)
+ .clampMaxNumElements(0, s16, 8)
+ .clampMaxNumElements(0, s32, 4)
+ .clampMaxNumElements(0, s64, 2)
.customIf(IsPtrVecPred);
getActionDefinitionsBuilder(G_STORE)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
index 45732f6c9c7f..cc7e4cbef71e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -395,3 +395,99 @@ body: |
%ptr:_(p0) = COPY $x0
G_STORE %val(<4 x s64>), %ptr(p0) :: (store 32)
RET_ReallyLR
+...
+---
+name: load_32xs8
+alignment: 4
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.1:
+ liveins: $x0
+ ; CHECK-LABEL: name: load_32xs8
+ ; CHECK: liveins: $x0
+ ; CHECK: %ptr:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD %ptr(p0) :: (load 16, align 32)
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[PTR_ADD]](p0) :: (load 16 + 16)
+ ; CHECK: G_STORE [[LOAD]](<16 x s8>), %ptr(p0) :: (store 16, align 32)
+ ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK: G_STORE [[LOAD1]](<16 x s8>), [[PTR_ADD1]](p0) :: (store 16 + 16)
+ ; CHECK: RET_ReallyLR
+ %ptr:_(p0) = COPY $x0
+ %val:_(<32 x s8>) = G_LOAD %ptr(p0) :: (load 32)
+ G_STORE %val(<32 x s8>), %ptr(p0) :: (store 32)
+ RET_ReallyLR
+...
+---
+name: load_16xs16
+alignment: 4
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.1:
+ liveins: $x0
+ ; CHECK-LABEL: name: load_16xs16
+ ; CHECK: liveins: $x0
+ ; CHECK: %ptr:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD %ptr(p0) :: (load 16, align 32)
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[PTR_ADD]](p0) :: (load 16 + 16)
+ ; CHECK: G_STORE [[LOAD]](<8 x s16>), %ptr(p0) :: (store 16, align 32)
+ ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK: G_STORE [[LOAD1]](<8 x s16>), [[PTR_ADD1]](p0) :: (store 16 + 16)
+ ; CHECK: RET_ReallyLR
+ %ptr:_(p0) = COPY $x0
+ %val:_(<16 x s16>) = G_LOAD %ptr(p0) :: (load 32)
+ G_STORE %val(<16 x s16>), %ptr(p0) :: (store 32)
+ RET_ReallyLR
+...
+---
+name: load_8xs32
+alignment: 4
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.1:
+ liveins: $x0
+ ; CHECK-LABEL: name: load_8xs32
+ ; CHECK: liveins: $x0
+ ; CHECK: %ptr:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD %ptr(p0) :: (load 16, align 32)
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD]](p0) :: (load 16 + 16)
+ ; CHECK: G_STORE [[LOAD]](<4 x s32>), %ptr(p0) :: (store 16, align 32)
+ ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK: G_STORE [[LOAD1]](<4 x s32>), [[PTR_ADD1]](p0) :: (store 16 + 16)
+ ; CHECK: RET_ReallyLR
+ %ptr:_(p0) = COPY $x0
+ %val:_(<8 x s32>) = G_LOAD %ptr(p0) :: (load 32)
+ G_STORE %val(<8 x s32>), %ptr(p0) :: (store 32)
+ RET_ReallyLR
+...
+---
+name: load_4xs64
+alignment: 4
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.1:
+ liveins: $x0
+ ; CHECK-LABEL: name: load_4xs64
+ ; CHECK: liveins: $x0
+ ; CHECK: %ptr:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr(p0) :: (load 16, align 32)
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load 16 + 16)
+ ; CHECK: G_STORE [[LOAD]](<2 x s64>), %ptr(p0) :: (store 16, align 32)
+ ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK: G_STORE [[LOAD1]](<2 x s64>), [[PTR_ADD1]](p0) :: (store 16 + 16)
+ ; CHECK: RET_ReallyLR
+ %ptr:_(p0) = COPY $x0
+ %val:_(<4 x s64>) = G_LOAD %ptr(p0) :: (load 32)
+ G_STORE %val(<4 x s64>), %ptr(p0) :: (store 32)
+ RET_ReallyLR
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