[PATCH] D96210: [TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:5187
+          DAG.getConstant(EltBits, dl,
+                          getShiftAmountTy(MulVT, DAG.getDataLayout())));
+      return DAG.getNode(ISD::TRUNCATE, dl, VT, Y);
----------------
craig.topper wrote:
> RKSimon wrote:
> > Pre-legalization shift amount is always nasty - is there any chance that this can be out of range?
> MulVT here is a legal type so the shift should be legal. So I think the target better be returning a shift amount type that should cover all possible amounts.
Would getShiftAmountConstant be safer?


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  https://reviews.llvm.org/D96210/new/

https://reviews.llvm.org/D96210