[PATCH] D96210: [TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:5101
+      if (NVT.getSizeInBits() >= (2 * EltBits) &&
+          isOperationLegal(ISD::MUL, NVT)) {
+        MulVT = NVT;
----------------
Do we not have a legalization helper function that we can use?


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:5187
+          DAG.getConstant(EltBits, dl,
+                          getShiftAmountTy(MulVT, DAG.getDataLayout())));
+      return DAG.getNode(ISD::TRUNCATE, dl, VT, Y);
----------------
Pre-legalization shift amount is always nasty - is there any chance that this can be out of range?


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Comment at: llvm/test/CodeGen/AArch64/urem-seteq.ll:86
+; CHECK-NEXT:    mov w9, #14
+; CHECK-NEXT:    msub w8, w8, w9, w0
+; CHECK-NEXT:    tst w8, #0xffff
----------------
No idea why but its odd that we now match a multiply-subtract here but lose the multiply-add in urem-seteq-nonzero.ll above


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D96210/new/

https://reviews.llvm.org/D96210