[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Jim Lin via Phabricator via llvm-commits]

Jim added inline comments.


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Comment at: llvm/docs/CommandGuide/tblgen.rst:141
 
-  Generate RISCV compressed instructions.
+  Generate RISC-V compressed instructions.
 
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It is typo fix. Could you fix it in a separate patch?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95016/new/

https://reviews.llvm.org/D95016