[PATCH] D92405: [VirtRegRewriter] Insert missing killed flags when tracking subregister liveness

[Baptiste Saleil via Phabricator via llvm-commits]

bsaleil added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll:19
 ; GFX9-FLATSCR: scratch_store_dwordx4 off, v[{{[0-9:]+}}], [[SOFF1]] ; 16-byte Folded Spill
-; GFX9-FLATSCR: s_movk_i32 [[SOFF2:s[0-9]+]], 0x{{[0-9a-f]+}}{{$}}
+; GFX9-FLATSCR: s_movk_i32 [[SOFF2:s[0-9]+]], 0x1{{[0-9a-f]+}}{{$}}
 ; GFX9-FLATSCR: scratch_load_dwordx4 v[{{[0-9:]+}}], off, [[SOFF2]] ; 16-byte Folded Reload
----------------
foad wrote:
> Why do you need this change?
@foad, If I understand correctly the test case, the generated code is divided in two parts, spills and reloads.
The two first check lines (`s_mov_b32` and `scratch_store_dwordx4`) are supposed to match a spill, the two other check lines (`s_movk_i32` and `scratch_load_dwordx4`) are supposed to match a reload.
Currently, the first two check lines are correctly matched in the spills part.
But `s_movk_i32` is actually also matched in the spills section. It turns out that there is a `scratch_load_dwordx4` for that same register in the reload part, so the test succeeds.
This patch modifies a bit the register allocation for this test case and now there is no `scratch_load_dwordx4` for that register.
By adding the 1 here, we force the `s_movk_i32` to be matched in the reload section because no `s_movk_i32` uses `0x1` in the spills section.
Then, the `scratch_load_dwordx4` for that register is correctly matched.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92405/new/

https://reviews.llvm.org/D92405