[PATCH] D96335: [NFC] Adding test for clobbering of high registers in Thumb

[Lucas Prates via Phabricator via llvm-commits]

pratlucas created this revision.
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Prior to the changes from D52010 <https://reviews.llvm.org/D52010>, clobbering Thumb's high registers in
inline asm would cause incorrect code to be generated - or an assertion
failure for debug builds. Now that the issue is no longer reproducible,
this patch adds a MIR test to cover that scenario.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96335

Files:
  llvm/test/CodeGen/Thumb/high-reg-clobber.mir


Index: llvm/test/CodeGen/Thumb/high-reg-clobber.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Thumb/high-reg-clobber.mir
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -run-pass regallocbasic %s -o - | FileCheck %s
+# RUN: llc -run-pass greedy %s -o - | FileCheck %s
+# RUN: llc -run-pass regallocfast %s -o - | FileCheck %s --check-prefix=FAST
+
+--- |
+  ; ModuleID = 'test.c'
+  source_filename = "test.c"
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv6m-arm-none-eabi"
+
+  define dso_local void @constraint_h(i32 %i) {
+  entry:
+    %i.addr = alloca i32, align 4
+    store i32 %i, i32* %i.addr, align 4
+    %0 = load i32, i32* %i.addr, align 4
+    call void asm sideeffect "mov r12, $0", "h,~{r12}"(i32 %0)
+    ret void
+  }
+
+...
+---
+name:            constraint_h
+alignment:       2
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: tgpr }
+  - { id: 1, class: hgpr }
+  - { id: 2, class: tgpr }
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+frameInfo:
+  maxAlignment:    4
+  maxCallFrameSize: 0
+  localFrameSize:  4
+stack:
+  - { id: 0, name: i.addr, size: 4, alignment: 4, local-offset: -4 }
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $r0
+
+    ; CHECK-LABEL: name: constraint_h
+    ; CHECK: liveins: $r0
+    ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
+    ; CHECK: tSTRspi [[COPY]], %stack.0.i.addr, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.i.addr)
+    ; CHECK: [[tLDRspi:%[0-9]+]]:tgpr = tLDRspi %stack.0.i.addr, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from %ir.i.addr)
+    ; CHECK: [[COPY1:%[0-9]+]]:hgpr = COPY [[tLDRspi]]
+    ; CHECK: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnoip_and_GPRwithAPSR_NZCVnosp */, [[COPY1]], 12 /* clobber */, implicit-def early-clobber $r12
+    ; CHECK: tBX_RET 14 /* CC::al */, $noreg
+    ; FAST-LABEL: name: constraint_h
+    ; FAST: liveins: $r0
+    ; FAST: tSTRspi killed renamable $r0, %stack.0.i.addr, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.i.addr)
+    ; FAST: renamable $r0 = tLDRspi %stack.0.i.addr, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from %ir.i.addr)
+    ; FAST: renamable $r8 = COPY killed renamable $r0
+    ; FAST: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnoip_and_GPRwithAPSR_NZCVnosp */, killed renamable $r8, 12 /* clobber */, implicit-def dead early-clobber $r12
+    ; FAST: tBX_RET 14 /* CC::al */, $noreg
+    %0:tgpr = COPY $r0
+    tSTRspi %0, %stack.0.i.addr, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.i.addr)
+    %2:tgpr = tLDRspi %stack.0.i.addr, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from %ir.i.addr)
+    %1:hgpr = COPY %2
+    INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:hGPR */, %1, 12 /* clobber */, implicit-def early-clobber $r12
+    tBX_RET 14 /* CC::al */, $noreg
+
+...


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