[PATCH] D94229: [RISCV] Implement vlseg intrinsics.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:994
+class VPseudoUSSegLoadMask<VReg RetClass, bits<11> EEW>:
+      Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+             (ins GetVRegNoV0<RetClass>.R:$merge, GPR:$rs1,
----------------
rogfer01 wrote:
> Hi Kai, sorry for digging up this now: it didn't occur to me before.
> 
> I understand `GetVRegNoV0` receives as `RetClass` a tuple register class. However `GetVRegNoV0` does not seem to handle these register classes and returns the same register class it was given. So I think we could end doing a register allocation like this
> 
> ```
> vsetvli a1, a1, e32,m2,ta,mu
> vlseg2e32.v v0, (a0), v0.t
> ```
> 
> which I would say is invalid.
> 
> What do you think? Thanks!
Thanks.

You are right. GetVRegNoV0 does not handle tuple register classes. It will be wrong if we reuse v0 in masked segment load/store instructions. Maybe we need to create tuple register classes without v0.


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  https://reviews.llvm.org/D94229/new/

https://reviews.llvm.org/D94229