[PATCH] D96263: [RISCV] Support scalable-vector masked gather operations

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1755
+// indexing is extended to the XLEN value type and scaled accordingly.
+SDValue RISCVTargetLowering::lowerMGATHER(SDValue Op, SelectionDAG &DAG) const {
+  MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
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I'll add tests in case LLVM tries to create "ext loads" out of these. We'd have to undo that if that were the case.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:92
+  // Load
+  def : Pat<(vti.Vector (riscv_mgather (vti.Vector GetVRegNoV0<vti.RegClass>.R:$merge),
+                                       RVVBaseAddr:$rs1,
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We can improve codegen for when the mask is known "true".


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:420
+    if !gt(octuple_elmul, 0) then {
+      if !le(octuple_elmul, 64) then {
+        defvar elmul_str = octuple_to_str<octuple_elmul>.ret;
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This is (helpfully) copy/pasted from VPseudos.td. Is there a way to create a "list" (e.g. of val/idx tuples) there which we reuse here?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D96263/new/

https://reviews.llvm.org/D96263