[PATCH] D96118: [AMDGPU][MC][GFX10] Improved errors reporting for invalid MIMG NSA operands

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG168ccc8ecb65: [AMDGPU][MC][GFX10] Improved errors reporting for invalid MIMG NSA operands (authored by dp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96118/new/

https://reviews.llvm.org/D96118

Files:
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/test/MC/AMDGPU/gfx10_err_pos.s


Index: llvm/test/MC/AMDGPU/gfx10_err_pos.s
===================================================================
--- llvm/test/MC/AMDGPU/gfx10_err_pos.s
+++ llvm/test/MC/AMDGPU/gfx10_err_pos.s
@@ -295,6 +295,16 @@
 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s1
 // CHECK-NEXT:{{^}}                          ^
 
+image_load_mip v[253:255], [v255, v254 dmask:0xe dim:1D
+// CHECK: error: expected a comma or a closing square bracket
+// CHECK-NEXT:{{^}}image_load_mip v[253:255], [v255, v254 dmask:0xe dim:1D
+// CHECK-NEXT:{{^}}                                       ^
+
+image_load_mip v[253:255], [v255, v254
+// CHECK: error: expected a comma or a closing square bracket
+// CHECK-NEXT:{{^}}image_load_mip v[253:255], [v255, v254
+// CHECK-NEXT:{{^}}                                      ^
+
 //==============================================================================
 // expected a counter name
 
@@ -342,6 +352,19 @@
 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:
 // CHECK-NEXT:{{^}}                               ^
 
+//==============================================================================
+// expected a register
+
+image_load v[0:3], [v4, v5, 6], s[8:15] dmask:0xf dim:3D unorm
+// CHECK: error: expected a register
+// CHECK-NEXT:{{^}}image_load v[0:3], [v4, v5, 6], s[8:15] dmask:0xf dim:3D unorm
+// CHECK-NEXT:{{^}}                            ^
+
+image_load v[0:3], [v4, v5, v], s[8:15] dmask:0xf dim:3D unorm
+// CHECK: error: expected a register
+// CHECK-NEXT:{{^}}image_load v[0:3], [v4, v5, v], s[8:15] dmask:0xf dim:3D unorm
+// CHECK-NEXT:{{^}}                            ^
+
 //==============================================================================
 // expected a register or a list of registers
 
Index: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -4882,16 +4882,21 @@
     unsigned Prefix = Operands.size();
 
     for (;;) {
+      auto Loc = getLoc();
       ResTy = parseReg(Operands);
+      if (ResTy == MatchOperand_NoMatch)
+        Error(Loc, "expected a register");
       if (ResTy != MatchOperand_Success)
-        return ResTy;
+        return MatchOperand_ParseFail;
 
       RBraceLoc = getLoc();
       if (trySkipToken(AsmToken::RBrac))
         break;
 
-      if (!trySkipToken(AsmToken::Comma))
+      if (!skipToken(AsmToken::Comma,
+                     "expected a comma or a closing square bracket")) {
         return MatchOperand_ParseFail;
+      }
     }
 
     if (Operands.size() - Prefix > 1) {


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D96118.322066.patch
Type: text/x-patch
Size: 2668 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210208/2563478c/attachment.bin>