[llvm] 859e66f - [Sparc] Fix multiclass template parameter types. NFC.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-02-06T15:33:09Z
New Revision: 859e66ff55670d81c58a9469300596a8493e8d5c

URL: https://github.com/llvm/llvm-project/commit/859e66ff55670d81c58a9469300596a8493e8d5c
DIFF: https://github.com/llvm/llvm-project/commit/859e66ff55670d81c58a9469300596a8493e8d5c.diff

LOG: [Sparc] Fix multiclass template parameter types. NFC.

Fixes TableGen parser errors reported by D95874.

Added: 
    

Modified: 
    llvm/lib/Target/Sparc/SparcInstrFormats.td

Removed: 
    


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diff  --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td b/llvm/lib/Target/Sparc/SparcInstrFormats.td
index da53307bcb1c..259ce967f2df 100644
--- a/llvm/lib/Target/Sparc/SparcInstrFormats.td
+++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td
@@ -224,7 +224,7 @@ class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
 
 // Define rr and ri shift instructions with patterns.
 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
-                ValueType VT, ValueType SIT, RegisterClass RC,
+                ValueType VT, Operand SIT, RegisterClass RC,
                 InstrItinClass itin = IIC_iu_instr> {
   def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
                  !strconcat(OpcStr, " $rs1, $rs2, $rd"),
@@ -237,7 +237,7 @@ multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
 }
 
 class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern,
-           InstrItinClass itin = NoItinerary>
+         InstrItinClass itin = NoItinerary>
    : InstSP<outs, ins, asmstr, pattern, itin> {
   bits<5> rd;