[PATCH] D94229: [RISCV] Implement vlseg intrinsics.

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added inline comments.
Herald added subscribers: StephenFan, vkmr.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:994
+class VPseudoUSSegLoadMask<VReg RetClass, bits<11> EEW>:
+      Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+             (ins GetVRegNoV0<RetClass>.R:$merge, GPR:$rs1,
----------------
Hi Kai, sorry for digging up this now: it didn't occur to me before.

I understand `GetVRegNoV0` receives as `RetClass` a tuple register class. However `GetVRegNoV0` does not seem to handle these register classes and returns the same register class it was given. So I think we could end doing a register allocation like this

```
vsetvli a1, a1, e32,m2,ta,mu
vlseg2e32.v v0, (a0), v0.t
```

which I would say is invalid.

What do you think? Thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94229/new/

https://reviews.llvm.org/D94229