[llvm] 3c767b9 - [RISCV] Correct types in tablegen multiclasses found by D95874.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Fri Feb 5 11:56:26 PST 2021


Author: Craig Topper
Date: 2021-02-05T11:55:58-08:00
New Revision: 3c767b96dcc54f9a19d38e9da1b48c20d0840c7a

URL: https://github.com/llvm/llvm-project/commit/3c767b96dcc54f9a19d38e9da1b48c20d0840c7a
DIFF: https://github.com/llvm/llvm-project/commit/3c767b96dcc54f9a19d38e9da1b48c20d0840c7a.diff

LOG: [RISCV] Correct types in tablegen multiclasses found by D95874.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 8e0fd5dfa173..0bd2643fd1e2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -52,7 +52,7 @@ def SDTRVVVecReduce : SDTypeProfile<1, 2, [
 foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR"] in
   def rvv_vecreduce_#kind : SDNode<"RISCVISD::VECREDUCE_"#kind, SDTRVVVecReduce>;
 
-multiclass VPatUSLoadStoreSDNode<LLVMType type,
+multiclass VPatUSLoadStoreSDNode<ValueType type,
                                  int sew,
                                  LMULInfo vlmul,
                                  OutPatFrag avl,


        


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