[llvm] 3d10a0b - [Reassociate] add test for shl+or; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2021-02-05T14:25:19-05:00
New Revision: 3d10a0bdabaa2446dd154e1481bfd2e464910a0e

URL: https://github.com/llvm/llvm-project/commit/3d10a0bdabaa2446dd154e1481bfd2e464910a0e
DIFF: https://github.com/llvm/llvm-project/commit/3d10a0bdabaa2446dd154e1481bfd2e464910a0e.diff

LOG: [Reassociate] add test for shl+or; NFC

Added: 
    

Modified: 
    llvm/test/Transforms/Reassociate/add-like-or.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/Reassociate/add-like-or.ll b/llvm/test/Transforms/Reassociate/add-like-or.ll
index dec1b3f82f49..757a10c03ce0 100644
--- a/llvm/test/Transforms/Reassociate/add-like-or.ll
+++ b/llvm/test/Transforms/Reassociate/add-like-or.ll
@@ -1,6 +1,21 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -reassociate -S | FileCheck %s
 
+define i32 @shl_add(i8 %x) {
+; CHECK-LABEL: @shl_add(
+; CHECK-NEXT:    [[CONV:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw nsw i32 [[CONV]], 8
+; CHECK-NEXT:    [[SHL2:%.*]] = shl nuw nsw i32 [[CONV]], 16
+; CHECK-NEXT:    [[ADD:%.*]] = or i32 [[SHL]], [[SHL2]]
+; CHECK-NEXT:    ret i32 [[ADD]]
+;
+  %conv = zext i8 %x to i32
+  %shl = shl nuw nsw i32 %conv, 8
+  %shl2 = shl nuw nsw i32 %conv, 16
+  %add = or i32 %shl, %shl2
+  ret i32 %add
+}
+
 ; If we don't know that operands have no common bits set,
 ; we can't convert the `or` into an `add`.
 define i32 @test1(i32 %a, i32 %b) {