[PATCH] D96108: [RISCV] Add support for splat fixed length build_vectors using RVV.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Building on the fixed vector support from D95705 <https://reviews.llvm.org/D95705>

I've added ISD nodes for vmv.v.x and vfmv.v.f and switched to
lowering the intrinsics to it. This allows us to share the same
isel patterns for both.

This doesn't handle splats of i64 on RV32 yet. The build_vector
gets converted to a vXi32 build_vector+bitcast during type
legalization. Not sure the best way to handle this at the moment.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96108

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv64.ll

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