[llvm] 6b280ce - [RISCV] Use LLVMScalarOrSameVectorWidth to make avoid needing to mention the index type for vrgatherei16 intrinsics.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 4 20:29:58 PST 2021
Author: Craig Topper
Date: 2021-02-04T20:26:45-08:00
New Revision: 6b280ce34c13d78c951f381346ff6f73c34e5d28
URL: https://github.com/llvm/llvm-project/commit/6b280ce34c13d78c951f381346ff6f73c34e5d28
DIFF: https://github.com/llvm/llvm-project/commit/6b280ce34c13d78c951f381346ff6f73c34e5d28.diff
LOG: [RISCV] Use LLVMScalarOrSameVectorWidth to make avoid needing to mention the index type for vrgatherei16 intrinsics.
Add .vv to the intrinsic name to be consistent with D95979.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D95981
Added:
Modified:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index b71ecddb0c30..70ee298ac2f7 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -243,6 +243,20 @@ let TargetPrefix = "riscv" in {
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMVectorOfBitcastsToInt<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic;
+ // Input: (vector_in, int16_vector_in, vl)
+ class RISCVRGatherEI16VVNoMask
+ : Intrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, LLVMScalarOrSameVectorWidth<0, llvm_i16_ty>,
+ llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic;
+ // For destination vector type is the same as first and second source vector.
+ // Input: (vector_in, vector_in, int16_vector_in, vl)
+ class RISCVRGatherEI16VVMask
+ : Intrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, LLVMMatchType<0>,
+ LLVMScalarOrSameVectorWidth<0, llvm_i16_ty>,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic;
// For destination vector type is the same as first source vector, and the
// second operand is XLen.
// Input: (vector_in, xlen_in, vl)
@@ -719,6 +733,10 @@ let TargetPrefix = "riscv" in {
def "int_riscv_" # NAME : RISCVGatherVXNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVGatherVXMask;
}
+ multiclass RISCVRGatherEI16VV {
+ def "int_riscv_" # NAME : RISCVRGatherEI16VVNoMask;
+ def "int_riscv_" # NAME # "_mask" : RISCVRGatherEI16VVMask;
+ }
// ABX means the destination type(A) is
diff erent from the first source
// type(B). X means any type for the second source operand.
multiclass RISCVBinaryABX {
@@ -998,7 +1016,7 @@ let TargetPrefix = "riscv" in {
defm vrgather_vv : RISCVRGatherVV;
defm vrgather_vx : RISCVRGatherVX;
- defm vrgatherei16 : RISCVBinaryAAX;
+ defm vrgatherei16_vv : RISCVRGatherEI16VV;
def "int_riscv_vcompress" : RISCVUnaryAAMask;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 61e1576ac544..693c634383fe 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -4393,14 +4393,14 @@ let Predicates = [HasStdExtV, HasStdExtF] in {
let Predicates = [HasStdExtV] in {
defm "" : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
AllIntegerVectors, uimm5>;
- defm "" : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16", "PseudoVRGATHEREI16",
+ defm "" : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
/* eew */ 16, AllIntegerVectors>;
} // Predicates = [HasStdExtV]
let Predicates = [HasStdExtV, HasStdExtF] in {
defm "" : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
AllFloatVectors, uimm5>;
- defm "" : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16", "PseudoVRGATHEREI16",
+ defm "" : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
/* eew */ 16, AllFloatVectors>;
} // Predicates = [HasStdExtV, HasStdExtF]
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
index 50dcdded0287..f77186070169 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
@@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vrgatherei16.nxv1i8.nxv1i16(
+declare <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i16>,
i32);
-define <vscale x 1 x i8> @intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8_nxv1i16:
+define <vscale x 1 x i8> @intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.nxv1i8.nxv1i16(
+ %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i16> %1,
i32 %2)
@@ -22,21 +22,21 @@ entry:
ret <vscale x 1 x i8> %a
}
-declare <vscale x 1 x i8> @llvm.riscv.vrgatherei16.mask.nxv1i8.nxv1i16(
+declare <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i32);
-define <vscale x 1 x i8> @intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8_nxv1i16:
+define <vscale x 1 x i8> @intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.mask.nxv1i8.nxv1i16(
+ %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i16> %2,
@@ -46,20 +46,20 @@ entry:
ret <vscale x 1 x i8> %a
}
-declare <vscale x 2 x i8> @llvm.riscv.vrgatherei16.nxv2i8.nxv2i16(
+declare <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i16>,
i32);
-define <vscale x 2 x i8> @intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8_nxv2i16:
+define <vscale x 2 x i8> @intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.nxv2i8.nxv2i16(
+ %a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i16> %1,
i32 %2)
@@ -67,21 +67,21 @@ entry:
ret <vscale x 2 x i8> %a
}
-declare <vscale x 2 x i8> @llvm.riscv.vrgatherei16.mask.nxv2i8.nxv2i16(
+declare <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i32);
-define <vscale x 2 x i8> @intrinsic_vrgatherei16_mask_vv_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2i8_nxv2i8_nxv2i16:
+define <vscale x 2 x i8> @intrinsic_vrgatherei16_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.mask.nxv2i8.nxv2i16(
+ %a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 2 x i16> %2,
@@ -91,20 +91,20 @@ entry:
ret <vscale x 2 x i8> %a
}
-declare <vscale x 4 x i8> @llvm.riscv.vrgatherei16.nxv4i8.nxv4i16(
+declare <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i16>,
i32);
-define <vscale x 4 x i8> @intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8_nxv4i16:
+define <vscale x 4 x i8> @intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.nxv4i8.nxv4i16(
+ %a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i16> %1,
i32 %2)
@@ -112,21 +112,21 @@ entry:
ret <vscale x 4 x i8> %a
}
-declare <vscale x 4 x i8> @llvm.riscv.vrgatherei16.mask.nxv4i8.nxv4i16(
+declare <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i32);
-define <vscale x 4 x i8> @intrinsic_vrgatherei16_mask_vv_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i8_nxv4i8_nxv4i16:
+define <vscale x 4 x i8> @intrinsic_vrgatherei16_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.mask.nxv4i8.nxv4i16(
+ %a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i16> %2,
@@ -136,20 +136,20 @@ entry:
ret <vscale x 4 x i8> %a
}
-declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.nxv8i8.nxv8i16(
+declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i16>,
i32);
-define <vscale x 8 x i8> @intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8_nxv8i16:
+define <vscale x 8 x i8> @intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.nxv8i8.nxv8i16(
+ %a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i16> %1,
i32 %2)
@@ -157,21 +157,21 @@ entry:
ret <vscale x 8 x i8> %a
}
-declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.mask.nxv8i8.nxv8i16(
+declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i32);
-define <vscale x 8 x i8> @intrinsic_vrgatherei16_mask_vv_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i8_nxv8i8_nxv8i16:
+define <vscale x 8 x i8> @intrinsic_vrgatherei16_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.mask.nxv8i8.nxv8i16(
+ %a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i16> %2,
@@ -181,20 +181,20 @@ entry:
ret <vscale x 8 x i8> %a
}
-declare <vscale x 16 x i8> @llvm.riscv.vrgatherei16.nxv16i8.nxv16i16(
+declare <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i16>,
i32);
-define <vscale x 16 x i8> @intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8_nxv16i16:
+define <vscale x 16 x i8> @intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v26, v8, v12
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.nxv16i8.nxv16i16(
+ %a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i16> %1,
i32 %2)
@@ -202,21 +202,21 @@ entry:
ret <vscale x 16 x i8> %a
}
-declare <vscale x 16 x i8> @llvm.riscv.vrgatherei16.mask.nxv16i8.nxv16i16(
+declare <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i32);
-define <vscale x 16 x i8> @intrinsic_vrgatherei16_mask_vv_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i8_nxv16i8_nxv16i16:
+define <vscale x 16 x i8> @intrinsic_vrgatherei16_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.mask.nxv16i8.nxv16i16(
+ %a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i16> %2,
@@ -226,20 +226,20 @@ entry:
ret <vscale x 16 x i8> %a
}
-declare <vscale x 32 x i8> @llvm.riscv.vrgatherei16.nxv32i8.nxv32i16(
+declare <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i16>,
i32);
-define <vscale x 32 x i8> @intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8_nxv32i16:
+define <vscale x 32 x i8> @intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v28, v8, v16
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.nxv32i8.nxv32i16(
+ %a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i16> %1,
i32 %2)
@@ -247,21 +247,21 @@ entry:
ret <vscale x 32 x i8> %a
}
-declare <vscale x 32 x i8> @llvm.riscv.vrgatherei16.mask.nxv32i8.nxv32i16(
+declare <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i32);
-define <vscale x 32 x i8> @intrinsic_vrgatherei16_mask_vv_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i8_nxv32i8_nxv32i16:
+define <vscale x 32 x i8> @intrinsic_vrgatherei16_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.mask.nxv32i8.nxv32i16(
+ %a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i16> %2,
@@ -271,20 +271,20 @@ entry:
ret <vscale x 32 x i8> %a
}
-declare <vscale x 1 x i16> @llvm.riscv.vrgatherei16.nxv1i16.nxv1i16(
+declare <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i32);
-define <vscale x 1 x i16> @intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16_nxv1i16:
+define <vscale x 1 x i16> @intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.nxv1i16.nxv1i16(
+ %a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i32 %2)
@@ -292,21 +292,21 @@ entry:
ret <vscale x 1 x i16> %a
}
-declare <vscale x 1 x i16> @llvm.riscv.vrgatherei16.mask.nxv1i16.nxv1i16(
+declare <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i32);
-define <vscale x 1 x i16> @intrinsic_vrgatherei16_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i16_nxv1i16_nxv1i16:
+define <vscale x 1 x i16> @intrinsic_vrgatherei16_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.mask.nxv1i16.nxv1i16(
+ %a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
@@ -316,20 +316,20 @@ entry:
ret <vscale x 1 x i16> %a
}
-declare <vscale x 2 x i16> @llvm.riscv.vrgatherei16.nxv2i16.nxv2i16(
+declare <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i32);
-define <vscale x 2 x i16> @intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16_nxv2i16:
+define <vscale x 2 x i16> @intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.nxv2i16.nxv2i16(
+ %a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i32 %2)
@@ -337,21 +337,21 @@ entry:
ret <vscale x 2 x i16> %a
}
-declare <vscale x 2 x i16> @llvm.riscv.vrgatherei16.mask.nxv2i16.nxv2i16(
+declare <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i32);
-define <vscale x 2 x i16> @intrinsic_vrgatherei16_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2i16_nxv2i16_nxv2i16:
+define <vscale x 2 x i16> @intrinsic_vrgatherei16_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.mask.nxv2i16.nxv2i16(
+ %a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
@@ -361,20 +361,20 @@ entry:
ret <vscale x 2 x i16> %a
}
-declare <vscale x 4 x i16> @llvm.riscv.vrgatherei16.nxv4i16.nxv4i16(
+declare <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i32);
-define <vscale x 4 x i16> @intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16_nxv4i16:
+define <vscale x 4 x i16> @intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.nxv4i16.nxv4i16(
+ %a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i32 %2)
@@ -382,21 +382,21 @@ entry:
ret <vscale x 4 x i16> %a
}
-declare <vscale x 4 x i16> @llvm.riscv.vrgatherei16.mask.nxv4i16.nxv4i16(
+declare <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i32);
-define <vscale x 4 x i16> @intrinsic_vrgatherei16_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i16_nxv4i16_nxv4i16:
+define <vscale x 4 x i16> @intrinsic_vrgatherei16_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.mask.nxv4i16.nxv4i16(
+ %a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
@@ -406,20 +406,20 @@ entry:
ret <vscale x 4 x i16> %a
}
-declare <vscale x 8 x i16> @llvm.riscv.vrgatherei16.nxv8i16.nxv8i16(
+declare <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i32);
-define <vscale x 8 x i16> @intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16_nxv8i16:
+define <vscale x 8 x i16> @intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.nxv8i16.nxv8i16(
+ %a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i32 %2)
@@ -427,21 +427,21 @@ entry:
ret <vscale x 8 x i16> %a
}
-declare <vscale x 8 x i16> @llvm.riscv.vrgatherei16.mask.nxv8i16.nxv8i16(
+declare <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i32);
-define <vscale x 8 x i16> @intrinsic_vrgatherei16_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i16_nxv8i16_nxv8i16:
+define <vscale x 8 x i16> @intrinsic_vrgatherei16_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.mask.nxv8i16.nxv8i16(
+ %a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
@@ -451,20 +451,20 @@ entry:
ret <vscale x 8 x i16> %a
}
-declare <vscale x 16 x i16> @llvm.riscv.vrgatherei16.nxv16i16.nxv16i16(
+declare <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i32);
-define <vscale x 16 x i16> @intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16_nxv16i16:
+define <vscale x 16 x i16> @intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.nxv16i16.nxv16i16(
+ %a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i32 %2)
@@ -472,21 +472,21 @@ entry:
ret <vscale x 16 x i16> %a
}
-declare <vscale x 16 x i16> @llvm.riscv.vrgatherei16.mask.nxv16i16.nxv16i16(
+declare <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i32);
-define <vscale x 16 x i16> @intrinsic_vrgatherei16_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i16_nxv16i16_nxv16i16:
+define <vscale x 16 x i16> @intrinsic_vrgatherei16_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.mask.nxv16i16.nxv16i16(
+ %a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
@@ -496,20 +496,20 @@ entry:
ret <vscale x 16 x i16> %a
}
-declare <vscale x 32 x i16> @llvm.riscv.vrgatherei16.nxv32i16.nxv32i16(
+declare <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i32);
-define <vscale x 32 x i16> @intrinsic_vrgatherei16_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i16_nxv32i16_nxv32i16:
+define <vscale x 32 x i16> @intrinsic_vrgatherei16_vv_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vrgatherei16.vv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.nxv32i16.nxv32i16(
+ %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i32 %2)
@@ -517,15 +517,15 @@ entry:
ret <vscale x 32 x i16> %a
}
-declare <vscale x 32 x i16> @llvm.riscv.vrgatherei16.mask.nxv32i16.nxv32i16(
+declare <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i32);
-define <vscale x 32 x i16> @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16:
+define <vscale x 32 x i16> @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v24, (a0)
@@ -533,7 +533,7 @@ define <vscale x 32 x i16> @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv
; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.mask.nxv32i16.nxv32i16(
+ %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
@@ -543,20 +543,20 @@ entry:
ret <vscale x 32 x i16> %a
}
-declare <vscale x 1 x i32> @llvm.riscv.vrgatherei16.nxv1i32.nxv1i16(
+declare <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i16>,
i32);
-define <vscale x 1 x i32> @intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32_nxv1i16:
+define <vscale x 1 x i32> @intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.nxv1i32.nxv1i16(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i16> %1,
i32 %2)
@@ -564,21 +564,21 @@ entry:
ret <vscale x 1 x i32> %a
}
-declare <vscale x 1 x i32> @llvm.riscv.vrgatherei16.mask.nxv1i32.nxv1i16(
+declare <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i32);
-define <vscale x 1 x i32> @intrinsic_vrgatherei16_mask_vv_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i32_nxv1i32_nxv1i16:
+define <vscale x 1 x i32> @intrinsic_vrgatherei16_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.mask.nxv1i32.nxv1i16(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i16> %2,
@@ -588,20 +588,20 @@ entry:
ret <vscale x 1 x i32> %a
}
-declare <vscale x 4 x i32> @llvm.riscv.vrgatherei16.nxv4i32.nxv4i16(
+declare <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i16>,
i32);
-define <vscale x 4 x i32> @intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32_nxv4i16:
+define <vscale x 4 x i32> @intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.nxv4i32.nxv4i16(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i16> %1,
i32 %2)
@@ -609,21 +609,21 @@ entry:
ret <vscale x 4 x i32> %a
}
-declare <vscale x 4 x i32> @llvm.riscv.vrgatherei16.mask.nxv4i32.nxv4i16(
+declare <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i32);
-define <vscale x 4 x i32> @intrinsic_vrgatherei16_mask_vv_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i32_nxv4i32_nxv4i16:
+define <vscale x 4 x i32> @intrinsic_vrgatherei16_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.mask.nxv4i32.nxv4i16(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i16> %2,
@@ -633,20 +633,20 @@ entry:
ret <vscale x 4 x i32> %a
}
-declare <vscale x 8 x i32> @llvm.riscv.vrgatherei16.nxv8i32.nxv8i16(
+declare <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i16>,
i32);
-define <vscale x 8 x i32> @intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32_nxv8i16:
+define <vscale x 8 x i32> @intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.nxv8i32.nxv8i16(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i16> %1,
i32 %2)
@@ -654,21 +654,21 @@ entry:
ret <vscale x 8 x i32> %a
}
-declare <vscale x 8 x i32> @llvm.riscv.vrgatherei16.mask.nxv8i32.nxv8i16(
+declare <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i32);
-define <vscale x 8 x i32> @intrinsic_vrgatherei16_mask_vv_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i32_nxv8i32_nxv8i16:
+define <vscale x 8 x i32> @intrinsic_vrgatherei16_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.mask.nxv8i32.nxv8i16(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i16> %2,
@@ -678,20 +678,20 @@ entry:
ret <vscale x 8 x i32> %a
}
-declare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.nxv16i32.nxv16i16(
+declare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i16>,
i32);
-define <vscale x 16 x i32> @intrinsic_vrgatherei16_vv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i32_nxv16i32_nxv16i16:
+define <vscale x 16 x i32> @intrinsic_vrgatherei16_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vrgatherei16.vv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.nxv16i32.nxv16i16(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i16> %1,
i32 %2)
@@ -699,15 +699,15 @@ entry:
ret <vscale x 16 x i32> %a
}
-declare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.mask.nxv16i32.nxv16i16(
+declare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i32);
-define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16:
+define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu
; CHECK-NEXT: vle16.v v28, (a0)
@@ -715,7 +715,7 @@ define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv
; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.mask.nxv16i32.nxv16i16(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i16> %2,
@@ -725,20 +725,20 @@ entry:
ret <vscale x 16 x i32> %a
}
-declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.nxv1f16.nxv1i16(
+declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x i16>,
i32);
-define <vscale x 1 x half> @intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16_nxv1i16:
+define <vscale x 1 x half> @intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.nxv1f16.nxv1i16(
+ %a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x i16> %1,
i32 %2)
@@ -746,21 +746,21 @@ entry:
ret <vscale x 1 x half> %a
}
-declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.mask.nxv1f16.nxv1i16(
+declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i32);
-define <vscale x 1 x half> @intrinsic_vrgatherei16_mask_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1f16_nxv1f16_nxv1i16:
+define <vscale x 1 x half> @intrinsic_vrgatherei16_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.mask.nxv1f16.nxv1i16(
+ %a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
<vscale x 1 x i16> %2,
@@ -770,20 +770,20 @@ entry:
ret <vscale x 1 x half> %a
}
-declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.nxv2f16.nxv2i16(
+declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x i16>,
i32);
-define <vscale x 2 x half> @intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16_nxv2i16:
+define <vscale x 2 x half> @intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.nxv2f16.nxv2i16(
+ %a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x i16> %1,
i32 %2)
@@ -791,21 +791,21 @@ entry:
ret <vscale x 2 x half> %a
}
-declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.mask.nxv2f16.nxv2i16(
+declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i32);
-define <vscale x 2 x half> @intrinsic_vrgatherei16_mask_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2f16_nxv2f16_nxv2i16:
+define <vscale x 2 x half> @intrinsic_vrgatherei16_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.mask.nxv2f16.nxv2i16(
+ %a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
<vscale x 2 x i16> %2,
@@ -815,20 +815,20 @@ entry:
ret <vscale x 2 x half> %a
}
-declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.nxv4f16.nxv4i16(
+declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x i16>,
i32);
-define <vscale x 4 x half> @intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16_nxv4i16:
+define <vscale x 4 x half> @intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.nxv4f16.nxv4i16(
+ %a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x i16> %1,
i32 %2)
@@ -836,21 +836,21 @@ entry:
ret <vscale x 4 x half> %a
}
-declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.mask.nxv4f16.nxv4i16(
+declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i32);
-define <vscale x 4 x half> @intrinsic_vrgatherei16_mask_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f16_nxv4f16_nxv4i16:
+define <vscale x 4 x half> @intrinsic_vrgatherei16_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.mask.nxv4f16.nxv4i16(
+ %a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
<vscale x 4 x i16> %2,
@@ -860,20 +860,20 @@ entry:
ret <vscale x 4 x half> %a
}
-declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.nxv8f16.nxv8i16(
+declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x i16>,
i32);
-define <vscale x 8 x half> @intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16_nxv8i16:
+define <vscale x 8 x half> @intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.nxv8f16.nxv8i16(
+ %a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x i16> %1,
i32 %2)
@@ -881,21 +881,21 @@ entry:
ret <vscale x 8 x half> %a
}
-declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.mask.nxv8f16.nxv8i16(
+declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i32);
-define <vscale x 8 x half> @intrinsic_vrgatherei16_mask_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f16_nxv8f16_nxv8i16:
+define <vscale x 8 x half> @intrinsic_vrgatherei16_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.mask.nxv8f16.nxv8i16(
+ %a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
<vscale x 8 x i16> %2,
@@ -905,20 +905,20 @@ entry:
ret <vscale x 8 x half> %a
}
-declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.nxv16f16.nxv16i16(
+declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x i16>,
i32);
-define <vscale x 16 x half> @intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16_nxv16i16:
+define <vscale x 16 x half> @intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.nxv16f16.nxv16i16(
+ %a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x i16> %1,
i32 %2)
@@ -926,21 +926,21 @@ entry:
ret <vscale x 16 x half> %a
}
-declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.mask.nxv16f16.nxv16i16(
+declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i32);
-define <vscale x 16 x half> @intrinsic_vrgatherei16_mask_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f16_nxv16f16_nxv16i16:
+define <vscale x 16 x half> @intrinsic_vrgatherei16_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.mask.nxv16f16.nxv16i16(
+ %a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
<vscale x 16 x i16> %2,
@@ -950,20 +950,20 @@ entry:
ret <vscale x 16 x half> %a
}
-declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.nxv32f16.nxv32i16(
+declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x i16>,
i32);
-define <vscale x 32 x half> @intrinsic_vrgatherei16_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32f16_nxv32f16_nxv32i16:
+define <vscale x 32 x half> @intrinsic_vrgatherei16_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vrgatherei16.vv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.nxv32f16.nxv32i16(
+ %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16(
<vscale x 32 x half> %0,
<vscale x 32 x i16> %1,
i32 %2)
@@ -971,15 +971,15 @@ entry:
ret <vscale x 32 x half> %a
}
-declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.mask.nxv32f16.nxv32i16(
+declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i32);
-define <vscale x 32 x half> @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16:
+define <vscale x 32 x half> @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v24, (a0)
@@ -987,7 +987,7 @@ define <vscale x 32 x half> @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nx
; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.mask.nxv32f16.nxv32i16(
+ %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv32f16(
<vscale x 32 x half> %0,
<vscale x 32 x half> %1,
<vscale x 32 x i16> %2,
@@ -997,20 +997,20 @@ entry:
ret <vscale x 32 x half> %a
}
-declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.nxv1f32.nxv1i16(
+declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x i16>,
i32);
-define <vscale x 1 x float> @intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32_nxv1i16:
+define <vscale x 1 x float> @intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.nxv1f32.nxv1i16(
+ %a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x i16> %1,
i32 %2)
@@ -1018,21 +1018,21 @@ entry:
ret <vscale x 1 x float> %a
}
-declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.mask.nxv1f32.nxv1i16(
+declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i32);
-define <vscale x 1 x float> @intrinsic_vrgatherei16_mask_vv_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1f32_nxv1f32_nxv1i16:
+define <vscale x 1 x float> @intrinsic_vrgatherei16_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.mask.nxv1f32.nxv1i16(
+ %a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
<vscale x 1 x i16> %2,
@@ -1042,20 +1042,20 @@ entry:
ret <vscale x 1 x float> %a
}
-declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.nxv4f32.nxv4i16(
+declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x i16>,
i32);
-define <vscale x 4 x float> @intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32_nxv4i16:
+define <vscale x 4 x float> @intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.nxv4f32.nxv4i16(
+ %a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32(
<vscale x 4 x float> %0,
<vscale x 4 x i16> %1,
i32 %2)
@@ -1063,21 +1063,21 @@ entry:
ret <vscale x 4 x float> %a
}
-declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.mask.nxv4f32.nxv4i16(
+declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i32);
-define <vscale x 4 x float> @intrinsic_vrgatherei16_mask_vv_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f32_nxv4f32_nxv4i16:
+define <vscale x 4 x float> @intrinsic_vrgatherei16_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.mask.nxv4f32.nxv4i16(
+ %a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv4f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
<vscale x 4 x i16> %2,
@@ -1087,20 +1087,20 @@ entry:
ret <vscale x 4 x float> %a
}
-declare <vscale x 8 x float> @llvm.riscv.vrgatherei16.nxv8f32.nxv8i16(
+declare <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x i16>,
i32);
-define <vscale x 8 x float> @intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32_nxv8i16:
+define <vscale x 8 x float> @intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.nxv8f32.nxv8i16(
+ %a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.nxv8f32(
<vscale x 8 x float> %0,
<vscale x 8 x i16> %1,
i32 %2)
@@ -1108,21 +1108,21 @@ entry:
ret <vscale x 8 x float> %a
}
-declare <vscale x 8 x float> @llvm.riscv.vrgatherei16.mask.nxv8f32.nxv8i16(
+declare <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i32);
-define <vscale x 8 x float> @intrinsic_vrgatherei16_mask_vv_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f32_nxv8f32_nxv8i16:
+define <vscale x 8 x float> @intrinsic_vrgatherei16_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.mask.nxv8f32.nxv8i16(
+ %a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv8f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
<vscale x 8 x i16> %2,
@@ -1132,20 +1132,20 @@ entry:
ret <vscale x 8 x float> %a
}
-declare <vscale x 16 x float> @llvm.riscv.vrgatherei16.nxv16f32.nxv16i16(
+declare <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x i16>,
i32);
-define <vscale x 16 x float> @intrinsic_vrgatherei16_vv_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f32_nxv16f32_nxv16i16:
+define <vscale x 16 x float> @intrinsic_vrgatherei16_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vrgatherei16.vv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.nxv16f32.nxv16i16(
+ %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.nxv16f32(
<vscale x 16 x float> %0,
<vscale x 16 x i16> %1,
i32 %2)
@@ -1153,15 +1153,15 @@ entry:
ret <vscale x 16 x float> %a
}
-declare <vscale x 16 x float> @llvm.riscv.vrgatherei16.mask.nxv16f32.nxv16i16(
+declare <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i32);
-define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16:
+define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu
; CHECK-NEXT: vle16.v v28, (a0)
@@ -1169,7 +1169,7 @@ define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_n
; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.mask.nxv16f32.nxv16i16(
+ %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv16f32(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
<vscale x 16 x i16> %2,
@@ -1179,20 +1179,20 @@ entry:
ret <vscale x 16 x float> %a
}
-declare <vscale x 4 x double> @llvm.riscv.vrgatherei16.nxv4f64.nxv4i16(
+declare <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x i16>,
i32);
-define <vscale x 4 x double> @intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64_nxv4i16:
+define <vscale x 4 x double> @intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.nxv4f64.nxv4i16(
+ %a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.nxv4f64(
<vscale x 4 x double> %0,
<vscale x 4 x i16> %1,
i32 %2)
@@ -1200,21 +1200,21 @@ entry:
ret <vscale x 4 x double> %a
}
-declare <vscale x 4 x double> @llvm.riscv.vrgatherei16.mask.nxv4f64.nxv4i16(
+declare <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i32);
-define <vscale x 4 x double> @intrinsic_vrgatherei16_mask_vv_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f64_nxv4f64_nxv4i16:
+define <vscale x 4 x double> @intrinsic_vrgatherei16_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.mask.nxv4f64.nxv4i16(
+ %a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv4f64(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
<vscale x 4 x i16> %2,
@@ -1224,20 +1224,20 @@ entry:
ret <vscale x 4 x double> %a
}
-declare <vscale x 8 x double> @llvm.riscv.vrgatherei16.nxv8f64.nxv8i16(
+declare <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x i16>,
i32);
-define <vscale x 8 x double> @intrinsic_vrgatherei16_vv_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f64_nxv8f64_nxv8i16:
+define <vscale x 8 x double> @intrinsic_vrgatherei16_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vrgatherei16.vv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.nxv8f64.nxv8i16(
+ %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.nxv8f64(
<vscale x 8 x double> %0,
<vscale x 8 x i16> %1,
i32 %2)
@@ -1245,15 +1245,15 @@ entry:
ret <vscale x 8 x double> %a
}
-declare <vscale x 8 x double> @llvm.riscv.vrgatherei16.mask.nxv8f64.nxv8i16(
+declare <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i32);
-define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16:
+define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m2,ta,mu
; CHECK-NEXT: vle16.v v26, (a0)
@@ -1261,7 +1261,7 @@ define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv
; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.mask.nxv8f64.nxv8i16(
+ %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv8f64(
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
<vscale x 8 x i16> %2,
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
index db5e0efadfbb..b855559940eb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
@@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vrgatherei16.nxv1i8.nxv1i16(
+declare <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i16>,
i64);
-define <vscale x 1 x i8> @intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8_nxv1i16:
+define <vscale x 1 x i8> @intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.nxv1i8.nxv1i16(
+ %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i16> %1,
i64 %2)
@@ -22,21 +22,21 @@ entry:
ret <vscale x 1 x i8> %a
}
-declare <vscale x 1 x i8> @llvm.riscv.vrgatherei16.mask.nxv1i8.nxv1i16(
+declare <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i64);
-define <vscale x 1 x i8> @intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8_nxv1i16:
+define <vscale x 1 x i8> @intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.mask.nxv1i8.nxv1i16(
+ %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i16> %2,
@@ -46,20 +46,20 @@ entry:
ret <vscale x 1 x i8> %a
}
-declare <vscale x 2 x i8> @llvm.riscv.vrgatherei16.nxv2i8.nxv2i16(
+declare <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i16>,
i64);
-define <vscale x 2 x i8> @intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8_nxv2i16:
+define <vscale x 2 x i8> @intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.nxv2i8.nxv2i16(
+ %a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i16> %1,
i64 %2)
@@ -67,21 +67,21 @@ entry:
ret <vscale x 2 x i8> %a
}
-declare <vscale x 2 x i8> @llvm.riscv.vrgatherei16.mask.nxv2i8.nxv2i16(
+declare <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i64);
-define <vscale x 2 x i8> @intrinsic_vrgatherei16_mask_vv_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2i8_nxv2i8_nxv2i16:
+define <vscale x 2 x i8> @intrinsic_vrgatherei16_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.mask.nxv2i8.nxv2i16(
+ %a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 2 x i16> %2,
@@ -91,20 +91,20 @@ entry:
ret <vscale x 2 x i8> %a
}
-declare <vscale x 4 x i8> @llvm.riscv.vrgatherei16.nxv4i8.nxv4i16(
+declare <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i16>,
i64);
-define <vscale x 4 x i8> @intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8_nxv4i16:
+define <vscale x 4 x i8> @intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.nxv4i8.nxv4i16(
+ %a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i16> %1,
i64 %2)
@@ -112,21 +112,21 @@ entry:
ret <vscale x 4 x i8> %a
}
-declare <vscale x 4 x i8> @llvm.riscv.vrgatherei16.mask.nxv4i8.nxv4i16(
+declare <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
-define <vscale x 4 x i8> @intrinsic_vrgatherei16_mask_vv_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i8_nxv4i8_nxv4i16:
+define <vscale x 4 x i8> @intrinsic_vrgatherei16_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.mask.nxv4i8.nxv4i16(
+ %a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i16> %2,
@@ -136,20 +136,20 @@ entry:
ret <vscale x 4 x i8> %a
}
-declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.nxv8i8.nxv8i16(
+declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i16>,
i64);
-define <vscale x 8 x i8> @intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8_nxv8i16:
+define <vscale x 8 x i8> @intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.nxv8i8.nxv8i16(
+ %a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i16> %1,
i64 %2)
@@ -157,21 +157,21 @@ entry:
ret <vscale x 8 x i8> %a
}
-declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.mask.nxv8i8.nxv8i16(
+declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
-define <vscale x 8 x i8> @intrinsic_vrgatherei16_mask_vv_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i8_nxv8i8_nxv8i16:
+define <vscale x 8 x i8> @intrinsic_vrgatherei16_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.mask.nxv8i8.nxv8i16(
+ %a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i16> %2,
@@ -181,20 +181,20 @@ entry:
ret <vscale x 8 x i8> %a
}
-declare <vscale x 16 x i8> @llvm.riscv.vrgatherei16.nxv16i8.nxv16i16(
+declare <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i16>,
i64);
-define <vscale x 16 x i8> @intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8_nxv16i16:
+define <vscale x 16 x i8> @intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v26, v8, v12
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.nxv16i8.nxv16i16(
+ %a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i16> %1,
i64 %2)
@@ -202,21 +202,21 @@ entry:
ret <vscale x 16 x i8> %a
}
-declare <vscale x 16 x i8> @llvm.riscv.vrgatherei16.mask.nxv16i8.nxv16i16(
+declare <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i64);
-define <vscale x 16 x i8> @intrinsic_vrgatherei16_mask_vv_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i8_nxv16i8_nxv16i16:
+define <vscale x 16 x i8> @intrinsic_vrgatherei16_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.mask.nxv16i8.nxv16i16(
+ %a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i16> %2,
@@ -226,20 +226,20 @@ entry:
ret <vscale x 16 x i8> %a
}
-declare <vscale x 32 x i8> @llvm.riscv.vrgatherei16.nxv32i8.nxv32i16(
+declare <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i16>,
i64);
-define <vscale x 32 x i8> @intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8_nxv32i16:
+define <vscale x 32 x i8> @intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v28, v8, v16
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.nxv32i8.nxv32i16(
+ %a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i16> %1,
i64 %2)
@@ -247,21 +247,21 @@ entry:
ret <vscale x 32 x i8> %a
}
-declare <vscale x 32 x i8> @llvm.riscv.vrgatherei16.mask.nxv32i8.nxv32i16(
+declare <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i64);
-define <vscale x 32 x i8> @intrinsic_vrgatherei16_mask_vv_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i8_nxv32i8_nxv32i16:
+define <vscale x 32 x i8> @intrinsic_vrgatherei16_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.mask.nxv32i8.nxv32i16(
+ %a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i16> %2,
@@ -271,20 +271,20 @@ entry:
ret <vscale x 32 x i8> %a
}
-declare <vscale x 1 x i16> @llvm.riscv.vrgatherei16.nxv1i16.nxv1i16(
+declare <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i64);
-define <vscale x 1 x i16> @intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16_nxv1i16:
+define <vscale x 1 x i16> @intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.nxv1i16.nxv1i16(
+ %a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i64 %2)
@@ -292,21 +292,21 @@ entry:
ret <vscale x 1 x i16> %a
}
-declare <vscale x 1 x i16> @llvm.riscv.vrgatherei16.mask.nxv1i16.nxv1i16(
+declare <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i64);
-define <vscale x 1 x i16> @intrinsic_vrgatherei16_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i16_nxv1i16_nxv1i16:
+define <vscale x 1 x i16> @intrinsic_vrgatherei16_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.mask.nxv1i16.nxv1i16(
+ %a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
@@ -316,20 +316,20 @@ entry:
ret <vscale x 1 x i16> %a
}
-declare <vscale x 2 x i16> @llvm.riscv.vrgatherei16.nxv2i16.nxv2i16(
+declare <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i64);
-define <vscale x 2 x i16> @intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16_nxv2i16:
+define <vscale x 2 x i16> @intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.nxv2i16.nxv2i16(
+ %a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i64 %2)
@@ -337,21 +337,21 @@ entry:
ret <vscale x 2 x i16> %a
}
-declare <vscale x 2 x i16> @llvm.riscv.vrgatherei16.mask.nxv2i16.nxv2i16(
+declare <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i64);
-define <vscale x 2 x i16> @intrinsic_vrgatherei16_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2i16_nxv2i16_nxv2i16:
+define <vscale x 2 x i16> @intrinsic_vrgatherei16_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.mask.nxv2i16.nxv2i16(
+ %a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
@@ -361,20 +361,20 @@ entry:
ret <vscale x 2 x i16> %a
}
-declare <vscale x 4 x i16> @llvm.riscv.vrgatherei16.nxv4i16.nxv4i16(
+declare <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i64);
-define <vscale x 4 x i16> @intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16_nxv4i16:
+define <vscale x 4 x i16> @intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.nxv4i16.nxv4i16(
+ %a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i64 %2)
@@ -382,21 +382,21 @@ entry:
ret <vscale x 4 x i16> %a
}
-declare <vscale x 4 x i16> @llvm.riscv.vrgatherei16.mask.nxv4i16.nxv4i16(
+declare <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
-define <vscale x 4 x i16> @intrinsic_vrgatherei16_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i16_nxv4i16_nxv4i16:
+define <vscale x 4 x i16> @intrinsic_vrgatherei16_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.mask.nxv4i16.nxv4i16(
+ %a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
@@ -406,20 +406,20 @@ entry:
ret <vscale x 4 x i16> %a
}
-declare <vscale x 8 x i16> @llvm.riscv.vrgatherei16.nxv8i16.nxv8i16(
+declare <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i64);
-define <vscale x 8 x i16> @intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16_nxv8i16:
+define <vscale x 8 x i16> @intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.nxv8i16.nxv8i16(
+ %a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i64 %2)
@@ -427,21 +427,21 @@ entry:
ret <vscale x 8 x i16> %a
}
-declare <vscale x 8 x i16> @llvm.riscv.vrgatherei16.mask.nxv8i16.nxv8i16(
+declare <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
-define <vscale x 8 x i16> @intrinsic_vrgatherei16_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i16_nxv8i16_nxv8i16:
+define <vscale x 8 x i16> @intrinsic_vrgatherei16_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.mask.nxv8i16.nxv8i16(
+ %a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
@@ -451,20 +451,20 @@ entry:
ret <vscale x 8 x i16> %a
}
-declare <vscale x 16 x i16> @llvm.riscv.vrgatherei16.nxv16i16.nxv16i16(
+declare <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i64);
-define <vscale x 16 x i16> @intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16_nxv16i16:
+define <vscale x 16 x i16> @intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.nxv16i16.nxv16i16(
+ %a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i64 %2)
@@ -472,21 +472,21 @@ entry:
ret <vscale x 16 x i16> %a
}
-declare <vscale x 16 x i16> @llvm.riscv.vrgatherei16.mask.nxv16i16.nxv16i16(
+declare <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i64);
-define <vscale x 16 x i16> @intrinsic_vrgatherei16_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i16_nxv16i16_nxv16i16:
+define <vscale x 16 x i16> @intrinsic_vrgatherei16_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.mask.nxv16i16.nxv16i16(
+ %a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
@@ -496,20 +496,20 @@ entry:
ret <vscale x 16 x i16> %a
}
-declare <vscale x 32 x i16> @llvm.riscv.vrgatherei16.nxv32i16.nxv32i16(
+declare <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i64);
-define <vscale x 32 x i16> @intrinsic_vrgatherei16_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i16_nxv32i16_nxv32i16:
+define <vscale x 32 x i16> @intrinsic_vrgatherei16_vv_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vrgatherei16.vv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.nxv32i16.nxv32i16(
+ %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i64 %2)
@@ -517,15 +517,15 @@ entry:
ret <vscale x 32 x i16> %a
}
-declare <vscale x 32 x i16> @llvm.riscv.vrgatherei16.mask.nxv32i16.nxv32i16(
+declare <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i64);
-define <vscale x 32 x i16> @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16:
+define <vscale x 32 x i16> @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v24, (a0)
@@ -533,7 +533,7 @@ define <vscale x 32 x i16> @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv
; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.mask.nxv32i16.nxv32i16(
+ %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
@@ -543,20 +543,20 @@ entry:
ret <vscale x 32 x i16> %a
}
-declare <vscale x 1 x i32> @llvm.riscv.vrgatherei16.nxv1i32.nxv1i16(
+declare <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i16>,
i64);
-define <vscale x 1 x i32> @intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32_nxv1i16:
+define <vscale x 1 x i32> @intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.nxv1i32.nxv1i16(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i16> %1,
i64 %2)
@@ -564,21 +564,21 @@ entry:
ret <vscale x 1 x i32> %a
}
-declare <vscale x 1 x i32> @llvm.riscv.vrgatherei16.mask.nxv1i32.nxv1i16(
+declare <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i64);
-define <vscale x 1 x i32> @intrinsic_vrgatherei16_mask_vv_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i32_nxv1i32_nxv1i16:
+define <vscale x 1 x i32> @intrinsic_vrgatherei16_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.mask.nxv1i32.nxv1i16(
+ %a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i16> %2,
@@ -588,20 +588,20 @@ entry:
ret <vscale x 1 x i32> %a
}
-declare <vscale x 4 x i32> @llvm.riscv.vrgatherei16.nxv4i32.nxv4i16(
+declare <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i16>,
i64);
-define <vscale x 4 x i32> @intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32_nxv4i16:
+define <vscale x 4 x i32> @intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.nxv4i32.nxv4i16(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i16> %1,
i64 %2)
@@ -609,21 +609,21 @@ entry:
ret <vscale x 4 x i32> %a
}
-declare <vscale x 4 x i32> @llvm.riscv.vrgatherei16.mask.nxv4i32.nxv4i16(
+declare <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
-define <vscale x 4 x i32> @intrinsic_vrgatherei16_mask_vv_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i32_nxv4i32_nxv4i16:
+define <vscale x 4 x i32> @intrinsic_vrgatherei16_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.mask.nxv4i32.nxv4i16(
+ %a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i16> %2,
@@ -633,20 +633,20 @@ entry:
ret <vscale x 4 x i32> %a
}
-declare <vscale x 8 x i32> @llvm.riscv.vrgatherei16.nxv8i32.nxv8i16(
+declare <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i16>,
i64);
-define <vscale x 8 x i32> @intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32_nxv8i16:
+define <vscale x 8 x i32> @intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.nxv8i32.nxv8i16(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i16> %1,
i64 %2)
@@ -654,21 +654,21 @@ entry:
ret <vscale x 8 x i32> %a
}
-declare <vscale x 8 x i32> @llvm.riscv.vrgatherei16.mask.nxv8i32.nxv8i16(
+declare <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
-define <vscale x 8 x i32> @intrinsic_vrgatherei16_mask_vv_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i32_nxv8i32_nxv8i16:
+define <vscale x 8 x i32> @intrinsic_vrgatherei16_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.mask.nxv8i32.nxv8i16(
+ %a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i16> %2,
@@ -678,20 +678,20 @@ entry:
ret <vscale x 8 x i32> %a
}
-declare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.nxv16i32.nxv16i16(
+declare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i16>,
i64);
-define <vscale x 16 x i32> @intrinsic_vrgatherei16_vv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i32_nxv16i32_nxv16i16:
+define <vscale x 16 x i32> @intrinsic_vrgatherei16_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vrgatherei16.vv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.nxv16i32.nxv16i16(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i16> %1,
i64 %2)
@@ -699,15 +699,15 @@ entry:
ret <vscale x 16 x i32> %a
}
-declare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.mask.nxv16i32.nxv16i16(
+declare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i64);
-define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16:
+define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu
; CHECK-NEXT: vle16.v v28, (a0)
@@ -715,7 +715,7 @@ define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv
; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.mask.nxv16i32.nxv16i16(
+ %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i16> %2,
@@ -725,20 +725,20 @@ entry:
ret <vscale x 16 x i32> %a
}
-declare <vscale x 4 x i64> @llvm.riscv.vrgatherei16.nxv4i64.nxv4i16(
+declare <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i16>,
i64);
-define <vscale x 4 x i64> @intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64_nxv4i16:
+define <vscale x 4 x i64> @intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.nxv4i64.nxv4i16(
+ %a = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i16> %1,
i64 %2)
@@ -746,21 +746,21 @@ entry:
ret <vscale x 4 x i64> %a
}
-declare <vscale x 4 x i64> @llvm.riscv.vrgatherei16.mask.nxv4i64.nxv4i16(
+declare <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
-define <vscale x 4 x i64> @intrinsic_vrgatherei16_mask_vv_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i64_nxv4i64_nxv4i16:
+define <vscale x 4 x i64> @intrinsic_vrgatherei16_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.mask.nxv4i64.nxv4i16(
+ %a = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 4 x i16> %2,
@@ -770,20 +770,20 @@ entry:
ret <vscale x 4 x i64> %a
}
-declare <vscale x 8 x i64> @llvm.riscv.vrgatherei16.nxv8i64.nxv8i16(
+declare <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i16>,
i64);
-define <vscale x 8 x i64> @intrinsic_vrgatherei16_vv_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i64_nxv8i64_nxv8i16:
+define <vscale x 8 x i64> @intrinsic_vrgatherei16_vv_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vrgatherei16.vv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.nxv8i64.nxv8i16(
+ %a = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i16> %1,
i64 %2)
@@ -791,15 +791,15 @@ entry:
ret <vscale x 8 x i64> %a
}
-declare <vscale x 8 x i64> @llvm.riscv.vrgatherei16.mask.nxv8i64.nxv8i16(
+declare <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
-define <vscale x 8 x i64> @intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64_nxv8i16:
+define <vscale x 8 x i64> @intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m2,ta,mu
; CHECK-NEXT: vle16.v v26, (a0)
@@ -807,7 +807,7 @@ define <vscale x 8 x i64> @intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64_nxv8i1
; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.mask.nxv8i64.nxv8i16(
+ %a = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 8 x i16> %2,
@@ -817,20 +817,20 @@ entry:
ret <vscale x 8 x i64> %a
}
-declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.nxv1f16.nxv1i16(
+declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x i16>,
i64);
-define <vscale x 1 x half> @intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16_nxv1i16:
+define <vscale x 1 x half> @intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.nxv1f16.nxv1i16(
+ %a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x i16> %1,
i64 %2)
@@ -838,21 +838,21 @@ entry:
ret <vscale x 1 x half> %a
}
-declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.mask.nxv1f16.nxv1i16(
+declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i64);
-define <vscale x 1 x half> @intrinsic_vrgatherei16_mask_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1f16_nxv1f16_nxv1i16:
+define <vscale x 1 x half> @intrinsic_vrgatherei16_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.mask.nxv1f16.nxv1i16(
+ %a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
<vscale x 1 x i16> %2,
@@ -862,20 +862,20 @@ entry:
ret <vscale x 1 x half> %a
}
-declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.nxv2f16.nxv2i16(
+declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x i16>,
i64);
-define <vscale x 2 x half> @intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16_nxv2i16:
+define <vscale x 2 x half> @intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.nxv2f16.nxv2i16(
+ %a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x i16> %1,
i64 %2)
@@ -883,21 +883,21 @@ entry:
ret <vscale x 2 x half> %a
}
-declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.mask.nxv2f16.nxv2i16(
+declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i64);
-define <vscale x 2 x half> @intrinsic_vrgatherei16_mask_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2f16_nxv2f16_nxv2i16:
+define <vscale x 2 x half> @intrinsic_vrgatherei16_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.mask.nxv2f16.nxv2i16(
+ %a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
<vscale x 2 x i16> %2,
@@ -907,20 +907,20 @@ entry:
ret <vscale x 2 x half> %a
}
-declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.nxv4f16.nxv4i16(
+declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x i16>,
i64);
-define <vscale x 4 x half> @intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16_nxv4i16:
+define <vscale x 4 x half> @intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.nxv4f16.nxv4i16(
+ %a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x i16> %1,
i64 %2)
@@ -928,21 +928,21 @@ entry:
ret <vscale x 4 x half> %a
}
-declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.mask.nxv4f16.nxv4i16(
+declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
-define <vscale x 4 x half> @intrinsic_vrgatherei16_mask_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f16_nxv4f16_nxv4i16:
+define <vscale x 4 x half> @intrinsic_vrgatherei16_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.mask.nxv4f16.nxv4i16(
+ %a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
<vscale x 4 x i16> %2,
@@ -952,20 +952,20 @@ entry:
ret <vscale x 4 x half> %a
}
-declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.nxv8f16.nxv8i16(
+declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x i16>,
i64);
-define <vscale x 8 x half> @intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16_nxv8i16:
+define <vscale x 8 x half> @intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.nxv8f16.nxv8i16(
+ %a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x i16> %1,
i64 %2)
@@ -973,21 +973,21 @@ entry:
ret <vscale x 8 x half> %a
}
-declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.mask.nxv8f16.nxv8i16(
+declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
-define <vscale x 8 x half> @intrinsic_vrgatherei16_mask_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f16_nxv8f16_nxv8i16:
+define <vscale x 8 x half> @intrinsic_vrgatherei16_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.mask.nxv8f16.nxv8i16(
+ %a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
<vscale x 8 x i16> %2,
@@ -997,20 +997,20 @@ entry:
ret <vscale x 8 x half> %a
}
-declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.nxv16f16.nxv16i16(
+declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x i16>,
i64);
-define <vscale x 16 x half> @intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16_nxv16i16:
+define <vscale x 16 x half> @intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.nxv16f16.nxv16i16(
+ %a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x i16> %1,
i64 %2)
@@ -1018,21 +1018,21 @@ entry:
ret <vscale x 16 x half> %a
}
-declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.mask.nxv16f16.nxv16i16(
+declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i64);
-define <vscale x 16 x half> @intrinsic_vrgatherei16_mask_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f16_nxv16f16_nxv16i16:
+define <vscale x 16 x half> @intrinsic_vrgatherei16_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.mask.nxv16f16.nxv16i16(
+ %a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
<vscale x 16 x i16> %2,
@@ -1042,20 +1042,20 @@ entry:
ret <vscale x 16 x half> %a
}
-declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.nxv32f16.nxv32i16(
+declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x i16>,
i64);
-define <vscale x 32 x half> @intrinsic_vrgatherei16_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32f16_nxv32f16_nxv32i16:
+define <vscale x 32 x half> @intrinsic_vrgatherei16_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vrgatherei16.vv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.nxv32f16.nxv32i16(
+ %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16(
<vscale x 32 x half> %0,
<vscale x 32 x i16> %1,
i64 %2)
@@ -1063,15 +1063,15 @@ entry:
ret <vscale x 32 x half> %a
}
-declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.mask.nxv32f16.nxv32i16(
+declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i64);
-define <vscale x 32 x half> @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16:
+define <vscale x 32 x half> @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v24, (a0)
@@ -1079,7 +1079,7 @@ define <vscale x 32 x half> @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nx
; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.mask.nxv32f16.nxv32i16(
+ %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv32f16(
<vscale x 32 x half> %0,
<vscale x 32 x half> %1,
<vscale x 32 x i16> %2,
@@ -1089,20 +1089,20 @@ entry:
ret <vscale x 32 x half> %a
}
-declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.nxv1f32.nxv1i16(
+declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x i16>,
i64);
-define <vscale x 1 x float> @intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32_nxv1i16:
+define <vscale x 1 x float> @intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.nxv1f32.nxv1i16(
+ %a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x i16> %1,
i64 %2)
@@ -1110,21 +1110,21 @@ entry:
ret <vscale x 1 x float> %a
}
-declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.mask.nxv1f32.nxv1i16(
+declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i64);
-define <vscale x 1 x float> @intrinsic_vrgatherei16_mask_vv_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1f32_nxv1f32_nxv1i16:
+define <vscale x 1 x float> @intrinsic_vrgatherei16_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.mask.nxv1f32.nxv1i16(
+ %a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
<vscale x 1 x i16> %2,
@@ -1134,20 +1134,20 @@ entry:
ret <vscale x 1 x float> %a
}
-declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.nxv4f32.nxv4i16(
+declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x i16>,
i64);
-define <vscale x 4 x float> @intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32_nxv4i16:
+define <vscale x 4 x float> @intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.nxv4f32.nxv4i16(
+ %a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32(
<vscale x 4 x float> %0,
<vscale x 4 x i16> %1,
i64 %2)
@@ -1155,21 +1155,21 @@ entry:
ret <vscale x 4 x float> %a
}
-declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.mask.nxv4f32.nxv4i16(
+declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
-define <vscale x 4 x float> @intrinsic_vrgatherei16_mask_vv_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f32_nxv4f32_nxv4i16:
+define <vscale x 4 x float> @intrinsic_vrgatherei16_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.mask.nxv4f32.nxv4i16(
+ %a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv4f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
<vscale x 4 x i16> %2,
@@ -1179,20 +1179,20 @@ entry:
ret <vscale x 4 x float> %a
}
-declare <vscale x 8 x float> @llvm.riscv.vrgatherei16.nxv8f32.nxv8i16(
+declare <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x i16>,
i64);
-define <vscale x 8 x float> @intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32_nxv8i16:
+define <vscale x 8 x float> @intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.nxv8f32.nxv8i16(
+ %a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.nxv8f32(
<vscale x 8 x float> %0,
<vscale x 8 x i16> %1,
i64 %2)
@@ -1200,21 +1200,21 @@ entry:
ret <vscale x 8 x float> %a
}
-declare <vscale x 8 x float> @llvm.riscv.vrgatherei16.mask.nxv8f32.nxv8i16(
+declare <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
-define <vscale x 8 x float> @intrinsic_vrgatherei16_mask_vv_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f32_nxv8f32_nxv8i16:
+define <vscale x 8 x float> @intrinsic_vrgatherei16_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.mask.nxv8f32.nxv8i16(
+ %a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv8f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
<vscale x 8 x i16> %2,
@@ -1224,20 +1224,20 @@ entry:
ret <vscale x 8 x float> %a
}
-declare <vscale x 16 x float> @llvm.riscv.vrgatherei16.nxv16f32.nxv16i16(
+declare <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x i16>,
i64);
-define <vscale x 16 x float> @intrinsic_vrgatherei16_vv_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f32_nxv16f32_nxv16i16:
+define <vscale x 16 x float> @intrinsic_vrgatherei16_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vrgatherei16.vv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.nxv16f32.nxv16i16(
+ %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.nxv16f32(
<vscale x 16 x float> %0,
<vscale x 16 x i16> %1,
i64 %2)
@@ -1245,15 +1245,15 @@ entry:
ret <vscale x 16 x float> %a
}
-declare <vscale x 16 x float> @llvm.riscv.vrgatherei16.mask.nxv16f32.nxv16i16(
+declare <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i64);
-define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16:
+define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu
; CHECK-NEXT: vle16.v v28, (a0)
@@ -1261,7 +1261,7 @@ define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_n
; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.mask.nxv16f32.nxv16i16(
+ %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv16f32(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
<vscale x 16 x i16> %2,
@@ -1271,20 +1271,20 @@ entry:
ret <vscale x 16 x float> %a
}
-declare <vscale x 4 x double> @llvm.riscv.vrgatherei16.nxv4f64.nxv4i16(
+declare <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x i16>,
i64);
-define <vscale x 4 x double> @intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64_nxv4i16:
+define <vscale x 4 x double> @intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.nxv4f64.nxv4i16(
+ %a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.nxv4f64(
<vscale x 4 x double> %0,
<vscale x 4 x i16> %1,
i64 %2)
@@ -1292,21 +1292,21 @@ entry:
ret <vscale x 4 x double> %a
}
-declare <vscale x 4 x double> @llvm.riscv.vrgatherei16.mask.nxv4f64.nxv4i16(
+declare <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
-define <vscale x 4 x double> @intrinsic_vrgatherei16_mask_vv_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f64_nxv4f64_nxv4i16:
+define <vscale x 4 x double> @intrinsic_vrgatherei16_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.mask.nxv4f64.nxv4i16(
+ %a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv4f64(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
<vscale x 4 x i16> %2,
@@ -1316,20 +1316,20 @@ entry:
ret <vscale x 4 x double> %a
}
-declare <vscale x 8 x double> @llvm.riscv.vrgatherei16.nxv8f64.nxv8i16(
+declare <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x i16>,
i64);
-define <vscale x 8 x double> @intrinsic_vrgatherei16_vv_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f64_nxv8f64_nxv8i16:
+define <vscale x 8 x double> @intrinsic_vrgatherei16_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vrgatherei16.vv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.nxv8f64.nxv8i16(
+ %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.nxv8f64(
<vscale x 8 x double> %0,
<vscale x 8 x i16> %1,
i64 %2)
@@ -1337,15 +1337,15 @@ entry:
ret <vscale x 8 x double> %a
}
-declare <vscale x 8 x double> @llvm.riscv.vrgatherei16.mask.nxv8f64.nxv8i16(
+declare <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
-define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16:
+define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m2,ta,mu
; CHECK-NEXT: vle16.v v26, (a0)
@@ -1353,7 +1353,7 @@ define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv
; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
- %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.mask.nxv8f64.nxv8i16(
+ %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv8f64(
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
<vscale x 8 x i16> %2,
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