[PATCH] D95964: [AMDGPU] Add f16 to i1 CodeGen patterns.

[Wen-Heng (Jack) Chung via Phabricator via llvm-commits]

whchung added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir:123-126
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s16) = G_TRUNC %0
+    %2:vgpr(s32) = G_FPTOUI %1
+    %3:vgpr(s1)  = G_TRUNC %2
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arsenm wrote:
> Hmm. It looks like these patterns aren't working. The MIR register banks are also not what I would expect. I think this needs some up-front work in the legalizer/regbankselect to handle properly, and would need end to end IR tests
@arsenm I'll take a look into AMDGPULegalizerInfo and AMDGPURegisterBankInfo. I'm not that well-versed in these aspect so I may come up with questions initially.

For end-to-end IR tests, do you feel any additions to fptosi.f16.ll and fptoui.f16.ll in this patch needed?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95964/new/

https://reviews.llvm.org/D95964