[PATCH] D95870: [RISCV] Support the scalable-vector fadd reduction intrinsic

[Craig Topper via Phabricator via llvm-commits]

craig.topper requested changes to this revision.
craig.topper added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1731
+  SDValue ZeroIdx = DAG.getConstant(0, DL, Subtarget.getXLenVT());
+  SDValue ScalarInVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, M1VT,
+                                    DAG.getUNDEF(M1VT), ScalarVal, ZeroIdx);
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frasercrmck wrote:
> craig.topper wrote:
> > craig.topper wrote:
> > > I think ISD::SCALAR_TO_VECTOR is what we would more commonly use.
> > i guess we don't have a true scalar_to_vector instruction in RVV, i.e. an instruction that just moves a scalar register without being dependent on the previous vector register. So I think INSERT_VECTOR_ELT is ok.
> Yeah, tbh, I can see how it could go either way. Since the upper elements of SCALAR_TO_VECTOR are undefined I suppose we could define it as equivalent to a splat. But I don't think that's worth doing, and INSERT_VECTOR_ELT better matches the semantics of the "scalar" operands of these reductions.
Should we splat here like we do for the integer reductions?


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  https://reviews.llvm.org/D95870/new/

https://reviews.llvm.org/D95870