[llvm] b10df8f - [AVR] Fix up a few accidentally-regressed Generic CodeGen tests recently broken

[Dylan McKay via llvm-commits]

Author: Dylan McKay
Date: 2021-02-05T04:21:54+13:00
New Revision: b10df8f7a5948edec77f5b57b18cdd736323a5fd

URL: https://github.com/llvm/llvm-project/commit/b10df8f7a5948edec77f5b57b18cdd736323a5fd
DIFF: https://github.com/llvm/llvm-project/commit/b10df8f7a5948edec77f5b57b18cdd736323a5fd.diff

LOG: [AVR] Fix up a few accidentally-regressed Generic CodeGen tests recently broken

In 85e8e6246e0fcc62ba727e8fb5990f1a632125d0, these tests were modified
to work with AVR, but the regex matchers were finicky and required a
fix forward patch, being this.

Added: 
    

Modified: 
    llvm/test/CodeGen/Generic/MIRDebugify/locations-and-values.mir
    llvm/test/CodeGen/Generic/MIRStripDebug/all.mir
    llvm/test/CodeGen/Generic/MIRStripDebug/dont-strip-real-debug-info.mir
    llvm/test/CodeGen/Generic/MIRStripDebug/multiple-moduleflags.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/Generic/MIRDebugify/locations-and-values.mir b/llvm/test/CodeGen/Generic/MIRDebugify/locations-and-values.mir
index 13990caadfd3..5145349a3494 100644
--- a/llvm/test/CodeGen/Generic/MIRDebugify/locations-and-values.mir
+++ b/llvm/test/CodeGen/Generic/MIRDebugify/locations-and-values.mir
@@ -9,10 +9,10 @@
   define i32 @test(i32 %a, i32 %b) {
     %add = add i32 %a, 2
   ; ALL-NEXT:  %add = add i32 %a, 2, !dbg [[L1:![0-9]+]]
-  ; VALUE-NEXT: call {{(addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %add, metadata [[add:![0-9]+]], metadata !DIExpression()), !dbg [[L1]]
+  ; VALUE-NEXT: call{{( addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %add, metadata [[add:![0-9]+]], metadata !DIExpression()), !dbg [[L1]]
     %sub = sub i32 %add, %b
   ; ALL-NEXT: %sub = sub i32 %add, %b, !dbg [[L2:![0-9]+]]
-  ; VALUE-NEXT: call {{(addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %sub, metadata [[sub:![0-9]+]], metadata !DIExpression()), !dbg [[L2]]
+  ; VALUE-NEXT: call{{( addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %sub, metadata [[sub:![0-9]+]], metadata !DIExpression()), !dbg [[L2]]
   ; ALL-NEXT: ret i32 %sub, !dbg [[L3:![0-9]+]]
     ret i32 %sub
   }

diff  --git a/llvm/test/CodeGen/Generic/MIRStripDebug/all.mir b/llvm/test/CodeGen/Generic/MIRStripDebug/all.mir
index 489968851860..7af3dde811f1 100644
--- a/llvm/test/CodeGen/Generic/MIRStripDebug/all.mir
+++ b/llvm/test/CodeGen/Generic/MIRStripDebug/all.mir
@@ -11,7 +11,7 @@
     call void @llvm.dbg.value(metadata i32 %sub, metadata !11, metadata !DIExpression()), !dbg !13
     ret i32 %sub, !dbg !14
   }
-  ; CHECK-LABEL: define i32 @test(i32 %a, i32 %b) {{(addrspace\([0-9]+\))?}} {
+  ; CHECK-LABEL: define i32 @test(i32 %a, i32 %b) {{(addrspace\([0-9]+\) )?}}{
   ; CHECK-NEXT:    %add = add i32 %a, 2
   ; CHECK-NEXT:    %sub = sub i32 %add, %b
   ; CHECK-NEXT:    ret i32 %sub

diff  --git a/llvm/test/CodeGen/Generic/MIRStripDebug/dont-strip-real-debug-info.mir b/llvm/test/CodeGen/Generic/MIRStripDebug/dont-strip-real-debug-info.mir
index 6cc8c246f53b..329f3b0a55fa 100644
--- a/llvm/test/CodeGen/Generic/MIRStripDebug/dont-strip-real-debug-info.mir
+++ b/llvm/test/CodeGen/Generic/MIRStripDebug/dont-strip-real-debug-info.mir
@@ -11,11 +11,11 @@
     call void @llvm.dbg.value(metadata i32 %sub, metadata !9, metadata !DIExpression()), !dbg !11
     ret i32 %sub, !dbg !12
   }
-  ; CHECK-LABEL: define i32 @test(i32 %a, i32 %b) {{(addrspace\([0-9]+\))?}} !dbg !4 {
+  ; CHECK-LABEL: define i32 @test(i32 %a, i32 %b) {{(addrspace\([0-9]+\) )?}}!dbg !4 {
   ; CHECK-NEXT:    %add = add i32 %a, 2, !dbg !10
-  ; CHECK-NEXT:    call {{(addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %add, metadata !7, metadata !DIExpression()), !dbg !10
+  ; CHECK-NEXT:    call{{( addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %add, metadata !7, metadata !DIExpression()), !dbg !10
   ; CHECK-NEXT:    %sub = sub i32 %add, %b, !dbg !11
-  ; CHECK-NEXT:    call {{(addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %sub, metadata !9, metadata !DIExpression()), !dbg !11
+  ; CHECK-NEXT:    call{{( addrspace\([0-9]+\))?}} void @llvm.dbg.value(metadata i32 %sub, metadata !9, metadata !DIExpression()), !dbg !11
   ; CHECK-NEXT:    ret i32 %sub, !dbg !12
   ; CHECK-NEXT:  }
   

diff  --git a/llvm/test/CodeGen/Generic/MIRStripDebug/multiple-moduleflags.mir b/llvm/test/CodeGen/Generic/MIRStripDebug/multiple-moduleflags.mir
index df280cf0a48b..792e1d47a429 100644
--- a/llvm/test/CodeGen/Generic/MIRStripDebug/multiple-moduleflags.mir
+++ b/llvm/test/CodeGen/Generic/MIRStripDebug/multiple-moduleflags.mir
@@ -11,7 +11,7 @@
     call void @llvm.dbg.value(metadata i32 %sub, metadata !11, metadata !DIExpression()), !dbg !13
     ret i32 %sub, !dbg !14
   }
-  ; CHECK-LABEL: define i32 @test(i32 %a, i32 %b) {{(addrspace\([0-9]+\))?}} {
+  ; CHECK-LABEL: define i32 @test(i32 %a, i32 %b) {{(addrspace\([0-9]+\) )?}}{
   ; CHECK-NEXT:    %add = add i32 %a, 2
   ; CHECK-NEXT:    %sub = sub i32 %add, %b
   ; CHECK-NEXT:    ret i32 %sub