[PATCH] D95979: [RISCV] Split vrgather intrinsics into separate vrgather.vv and vrgather.vx intrinsics.

[Craig Topper via Phabricator via llvm-commits]

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The vrgather.vv instruction uses a vector of indices with the same
SEW as operand 0. The vrgather.vx instructions use a scalar index
operand of XLen bits.

By splitting this into 2 intrinsics we are able to use LLVMatchType
in the definition to avoid specifying the type for the index operand
when creating the IR for the intrinsic. For .vv it will match the
operand 0 type. And for .vx it will match the type of the vl operand
we already needed to specify a type for.

I'm considering splitting more intrinsics. This was a somewhat
odd one because the .vx doesn't use the element type, it always
use XLen.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95979

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll

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