[llvm] 1a13ee1 - [GlobalISel] Add sext(constant) -> constant artifact combine.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 3 14:10:33 PST 2021
Author: Amara Emerson
Date: 2021-02-03T14:10:08-08:00
New Revision: 1a13ee1efb62c048c5a38090fe9e64a09df23c03
URL: https://github.com/llvm/llvm-project/commit/1a13ee1efb62c048c5a38090fe9e64a09df23c03
DIFF: https://github.com/llvm/llvm-project/commit/1a13ee1efb62c048c5a38090fe9e64a09df23c03.diff
LOG: [GlobalISel] Add sext(constant) -> constant artifact combine.
This is the G_SEXT counterpart to the existing G_ZEXT/G_ANYEXT combines.
Differential Revision: https://reviews.llvm.org/D95729
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index 4b02eda26c5c..7d5e1c80b50f 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -81,7 +81,6 @@ class LegalizationArtifactCombiner {
}
// Try to fold aext(g_constant) when the larger constant type is legal.
- // Can't use MIPattern because we don't have a specific constant in mind.
auto *SrcMI = MRI.getVRegDef(SrcReg);
if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) {
const LLT DstTy = MRI.getType(DstReg);
@@ -142,7 +141,6 @@ class LegalizationArtifactCombiner {
}
// Try to fold zext(g_constant) when the larger constant type is legal.
- // Can't use MIPattern because we don't have a specific constant in mind.
auto *SrcMI = MRI.getVRegDef(SrcReg);
if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) {
const LLT DstTy = MRI.getType(DstReg);
@@ -197,6 +195,20 @@ class LegalizationArtifactCombiner {
return true;
}
+ // Try to fold sext(g_constant) when the larger constant type is legal.
+ auto *SrcMI = MRI.getVRegDef(SrcReg);
+ if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) {
+ const LLT DstTy = MRI.getType(DstReg);
+ if (isInstLegal({TargetOpcode::G_CONSTANT, {DstTy}})) {
+ auto &CstVal = SrcMI->getOperand(1);
+ Builder.buildConstant(
+ DstReg, CstVal.getCImm()->getValue().sext(DstTy.getSizeInBits()));
+ UpdatedDefs.push_back(DstReg);
+ markInstAndDefDead(MI, *SrcMI, DeadInsts);
+ return true;
+ }
+ }
+
return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs);
}
@@ -211,7 +223,6 @@ class LegalizationArtifactCombiner {
Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
// Try to fold trunc(g_constant) when the smaller constant type is legal.
- // Can't use MIPattern because we don't have a specific constant in mind.
auto *SrcMI = MRI.getVRegDef(SrcReg);
if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) {
const LLT DstTy = MRI.getType(DstReg);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
index bc3d049c7cdf..b1f218d22c2a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
@@ -8,9 +8,8 @@ body: |
liveins: $q0
; CHECK-LABEL: name: test_eve_1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[C]](s32)
- ; CHECK: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[SEXT]](s64)
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](s64)
; CHECK: $x0 = COPY [[EVEC]](s64)
; CHECK: RET_ReallyLR
%0:_(<2 x s64>) = COPY $q0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
index 7ff7952d062b..28ac01356521 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
@@ -54,7 +54,6 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
@@ -62,8 +61,8 @@ body: |
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
- ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s16)
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT]]
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[C]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
@@ -162,7 +161,6 @@ body: |
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
@@ -179,21 +177,21 @@ body: |
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 16
- ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C2]](s16)
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG4]](s32), [[SEXT]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY13]], 16
- ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C2]](s16)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG5]](s32), [[SEXT1]]
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG4]](s32), [[COPY13]]
+ ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
+ ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY14]], 16
+ ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG5]](s32), [[C2]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP2]], [[ICMP]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND2]](s32), [[AND3]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK: $vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<2 x s32>)
@@ -235,7 +233,6 @@ body: |
; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY6]], [[COPY7]]
; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
- ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
; CHECK: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
@@ -263,16 +260,16 @@ body: |
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY14]], 16
- ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C1]](s16)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG6]](s32), [[SEXT]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY15]], 16
- ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C1]](s16)
- ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG7]](s32), [[SEXT1]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY16]], 16
- ; CHECK: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[C1]](s16)
- ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG8]](s32), [[SEXT2]]
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG6]](s32), [[COPY15]]
+ ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
+ ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY16]], 16
+ ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG7]](s32), [[COPY17]]
+ ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
+ ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY18]], 16
+ ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG8]](s32), [[C1]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP4]], [[ICMP1]]
; CHECK: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[ICMP5]], [[ICMP2]]
@@ -287,35 +284,35 @@ body: |
; CHECK: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV13]](<2 x s16>)
; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C2]]
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C2]]
+ ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C2]]
+ ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C2]]
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C2]]
+ ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
+ ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C2]]
+ ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C2]]
+ ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C2]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>), [[BITCAST12]](<2 x s16>)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
+ ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
+ ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C3]]
+ ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND6]](s32), [[AND7]](s32), [[AND8]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
@@ -379,7 +376,6 @@ body: |
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
- ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
@@ -412,20 +408,20 @@ body: |
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY22]], 16
- ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C2]](s16)
- ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG8]](s32), [[SEXT]]
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY23]], 16
- ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C2]](s16)
- ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG9]](s32), [[SEXT1]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
- ; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY24]], 16
- ; CHECK: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[C2]](s16)
- ; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG10]](s32), [[SEXT2]]
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY25]], 16
- ; CHECK: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[C2]](s16)
- ; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG11]](s32), [[SEXT3]]
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG8]](s32), [[COPY23]]
+ ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
+ ; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY24]], 16
+ ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG9]](s32), [[COPY25]]
+ ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
+ ; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY26]], 16
+ ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG10]](s32), [[COPY27]]
+ ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
+ ; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY28]], 16
+ ; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG11]](s32), [[C2]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP4]], [[ICMP]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP5]], [[ICMP1]]
; CHECK: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[ICMP6]], [[ICMP2]]
@@ -435,14 +431,14 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR2]](s1)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR3]](s1)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C3]]
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C3]]
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
+ ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
+ ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C3]]
+ ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C3]]
+ ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND4]](s32), [[AND5]](s32), [[AND6]](s32), [[AND7]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; CHECK: $vgpr2_vgpr3_vgpr4_vgpr5 = COPY [[BUILD_VECTOR]](<4 x s32>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
index 142677ec7c4d..bce6a36f4686 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
@@ -54,7 +54,6 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
@@ -62,8 +61,8 @@ body: |
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
- ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s16)
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG2]](s32), [[SEXT]]
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG2]](s32), [[C]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
@@ -162,7 +161,6 @@ body: |
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
@@ -179,21 +177,21 @@ body: |
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 16
- ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C2]](s16)
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG4]](s32), [[SEXT]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY13]], 16
- ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C2]](s16)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG5]](s32), [[SEXT1]]
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG4]](s32), [[COPY13]]
+ ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
+ ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY14]], 16
+ ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG5]](s32), [[C2]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP2]], [[ICMP]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND2]](s32), [[AND3]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK: $vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<2 x s32>)
@@ -235,7 +233,6 @@ body: |
; CHECK: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY6]], [[COPY7]]
; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
- ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
; CHECK: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
@@ -263,16 +260,16 @@ body: |
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY14]], 16
- ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C1]](s16)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG6]](s32), [[SEXT]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY15]], 16
- ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C1]](s16)
- ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG7]](s32), [[SEXT1]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY16]], 16
- ; CHECK: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[C1]](s16)
- ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG8]](s32), [[SEXT2]]
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG6]](s32), [[COPY15]]
+ ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
+ ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY16]], 16
+ ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG7]](s32), [[COPY17]]
+ ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
+ ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY18]], 16
+ ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG8]](s32), [[C1]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP4]], [[ICMP1]]
; CHECK: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[ICMP5]], [[ICMP2]]
@@ -287,35 +284,35 @@ body: |
; CHECK: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV13]](<2 x s16>)
; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C2]]
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C2]]
+ ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C2]]
+ ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C2]]
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C2]]
+ ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
+ ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C2]]
+ ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C2]]
+ ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C2]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>), [[BITCAST12]](<2 x s16>)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
+ ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
+ ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C3]]
+ ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND6]](s32), [[AND7]](s32), [[AND8]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
@@ -379,7 +376,6 @@ body: |
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
- ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
@@ -412,20 +408,20 @@ body: |
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY22]], 16
- ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C2]](s16)
- ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG8]](s32), [[SEXT]]
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY23]], 16
- ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C2]](s16)
- ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG9]](s32), [[SEXT1]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
- ; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY24]], 16
- ; CHECK: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[C2]](s16)
- ; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG10]](s32), [[SEXT2]]
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY25]], 16
- ; CHECK: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[C2]](s16)
- ; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG11]](s32), [[SEXT3]]
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG8]](s32), [[COPY23]]
+ ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
+ ; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY24]], 16
+ ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG9]](s32), [[COPY25]]
+ ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
+ ; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY26]], 16
+ ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG10]](s32), [[COPY27]]
+ ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
+ ; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY28]], 16
+ ; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG11]](s32), [[C2]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP4]], [[ICMP]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP5]], [[ICMP1]]
; CHECK: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[ICMP6]], [[ICMP2]]
@@ -435,14 +431,14 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR2]](s1)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR3]](s1)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C3]]
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C3]]
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
+ ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
+ ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C3]]
+ ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C3]]
+ ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND4]](s32), [[AND5]](s32), [[AND6]](s32), [[AND7]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; CHECK: $vgpr2_vgpr3_vgpr4_vgpr5 = COPY [[BUILD_VECTOR]](<4 x s32>)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir
index 527ae08ea1bf..db4e58a2b85b 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir
@@ -33,10 +33,9 @@ body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_gep_i8
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 20
- ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s8)
- ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[SEXT]](s32)
- ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
+ ; CHECK: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
; CHECK: RET 0
%0(p0) = IMPLICIT_DEF
%1(s8) = G_CONSTANT i8 20
@@ -55,10 +54,9 @@ body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_gep_i16
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 20
- ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s16)
- ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[SEXT]](s32)
- ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
+ ; CHECK: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
; CHECK: RET 0
%0(p0) = IMPLICIT_DEF
%1(s16) = G_CONSTANT i16 20
@@ -78,8 +76,8 @@ body: |
; CHECK-LABEL: name: test_gep_i32
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
- ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
+ ; CHECK: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
; CHECK: RET 0
%0(p0) = IMPLICIT_DEF
%1(s32) = G_CONSTANT i32 20
@@ -99,8 +97,8 @@ body: |
; CHECK-LABEL: name: test_gep_i64
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
- ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s64)
- ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s64)
+ ; CHECK: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
; CHECK: RET 0
%0(p0) = IMPLICIT_DEF
%1(s64) = G_CONSTANT i64 20
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