[PATCH] D93300: [PowerPC] Exploit paddi instruction on Power 10 for constant materialization

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1095
+  if ((LZ + FO + TO) > 30) {
+    APInt SignedInt34 = APInt(34, (Imm >> TO) & 0x3ffffffff);
+    APInt Extended = SignedInt34.sext(64);
----------------
stefanp wrote:
> NeHuang wrote:
> > Can we merge the code for the three patterns? Maybe we can do something like: 
> > Var = TZ/30-LZ/TO for different scenarios and use Var below (feel free to change Var to other name):
> > 
> > ```
> >     APInt SignedInt34 = APInt(34, (Imm >> (Var)) & 0x3ffffffff);
> >     APInt Extended = SignedInt34.sext(64);
> >     Result = CurDAG->getMachineNode(PPC::PLI8, dl, MVT::i64,
> >                                     getI64Imm(*Extended.getRawData()));
> >     return CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, SDValue(Result, 0),
> >                                   getI32Imm(Var), getI32Imm(LZ));
> > ```
> That's a good idea. I'm going to try to merge these into one and see how that looks.
> I want to try to keep the comments to explain each scenario.
I realized now why this isn't going to work. I thought it was going to work when you mentioned it but now I see why they are separate.
The instructions are not identical. When the shift is TZ the instruction is RLDIC and the other two are RLDICL. I don't think it is worth changing how the code is written to merge just two of the patterns (it will make it more confusing when looking at why all the patterns have their own if statement and then two of them are merged) Therefore I'm just going to leave the code as-is.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93300/new/

https://reviews.llvm.org/D93300