[PATCH] D95964: [AMDGPU] Add f16 to i1 CodeGen patterns.

[Wen-Heng (Jack) Chung via Phabricator via llvm-commits]

whchung created this revision.
whchung added a reviewer: rampitec.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, arsenm.
whchung requested review of this revision.
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Follow patterns used for f32 and f64 types.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95964

Files:
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
  llvm/test/CodeGen/AMDGPU/fptoui.f16.ll


Index: llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
+++ llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
@@ -130,3 +130,16 @@
   store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r
   ret void
 }
+
+; GCN-LABEL: {{^}}fptoui_f16_to_i1:
+; SI: v_cvt_f32_f16_e32 v{{[0-9+]}}, s{{[0-9]+}}
+; SI: v_cmp_eq_f32_e32 vcc, 1.0, v{{[0-9]+}}
+; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
+; VI: v_cmp_eq_f16_e64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{[0-9]+}}
+; VI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, s[0:1]
+define amdgpu_kernel void @fptoui_f16_to_i1(i1 addrspace(1)* %out, half %in) {
+entry:
+  %conv = fptoui half %in to i1
+  store i1 %conv, i1 addrspace(1)* %out
+  ret void
+}
Index: llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
+++ llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
@@ -132,3 +132,16 @@
   store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r
   ret void
 }
+
+; GCN-LABEL: {{^}}fptosi_f16_to_i1:
+; SI: v_cvt_f32_f16_e32 v{{[0-9+]}}, s{{[0-9]+}}
+; SI: v_cmp_eq_f32_e32 vcc, -1.0, v{{[0-9]+}}
+; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
+; VI: v_cmp_eq_f16_e64 s{{\[[0-9]+:[0-9]+\]}}, 0xbc00, s{{[0-9]+}}
+; VI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, s[0:1]
+define amdgpu_kernel void @fptosi_f16_to_i1(i1 addrspace(1)* %out, half %in) {
+entry:
+  %conv = fptosi half %in to i1
+  store i1 %conv, i1 addrspace(1)* %out
+  ret void
+}
Index: llvm/lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstructions.td
+++ llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -1795,6 +1795,8 @@
   (i1 (Inst 0, (kone_type KOne), $src0_modifiers, $src0, DSTCLAMP.NONE))
 >;
 
+def : FPToI1Pat<V_CMP_EQ_F16_e64, CONST.FP16_ONE, i16, f16, fp_to_uint>;
+def : FPToI1Pat<V_CMP_EQ_F16_e64, CONST.FP16_NEG_ONE, i16, f16, fp_to_sint>;
 def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_ONE, i32, f32, fp_to_uint>;
 def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_NEG_ONE, i32, f32, fp_to_sint>;
 def : FPToI1Pat<V_CMP_EQ_F64_e64, CONST.FP64_ONE, i64, f64, fp_to_uint>;


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