[PATCH] D95705: [RISCV] Add initial support for converting fixed vectors to scalable vectors during lowering to use RVV instructions.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:60
   // Store
-  def : Pat<(store type:$rs2, reg_rs1:$rs1),
+  def : Pat<(store (type reg_class:$rs2), reg_rs1:$rs1),
             (store_instr reg_class:$rs2, reg_rs1:$rs1, avl, sew)>;
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Need rebase here.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:65
+    // Load
+    def : Pat<(vti.Vector (riscv_vle_vl reg_rs1:$rs1, (XLenVT GPR:$vl))),
+              (load_instr reg_rs1:$rs1, (NoX0 GPR:$vl), vti.SEW)>;
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Use RVVBaseAddr instead of reg_rs1.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-Zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-Zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
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small case for "experimental-zfh".


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll:3
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-Zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-Zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-Zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV32
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Do we need different check prefix for riscv32 and riscv64? That is LMULMAX2-RV32 and LMULMAX2-RV64.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D95705/new/

https://reviews.llvm.org/D95705