[llvm] 63baeec - [RISCV] Load/store vector mask types.

[Hsiangkai Wang via llvm-commits]

Author: Hsiangkai Wang
Date: 2021-02-03T13:44:15+08:00
New Revision: 63baeec66e7fd07c2085eee42663fae2b05a9917

URL: https://github.com/llvm/llvm-project/commit/63baeec66e7fd07c2085eee42663fae2b05a9917
DIFF: https://github.com/llvm/llvm-project/commit/63baeec66e7fd07c2085eee42663fae2b05a9917.diff

LOG: [RISCV] Load/store vector mask types.

Use vle1.v/vse1.v to load/store vector mask types.

Differential Revision: https://reviews.llvm.org/D93364

Added: 
    llvm/test/CodeGen/RISCV/rvv/load-mask.ll

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 24f2c3510128..3b0d04a277dd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -45,8 +45,7 @@ class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
    dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
 }
 
-multiclass VPatUSLoadStoreSDNode<ValueType type,
-                                 ValueType mask_type,
+multiclass VPatUSLoadStoreSDNode<LLVMType type,
                                  int sew,
                                  LMULInfo vlmul,
                                  OutPatFrag avl,
@@ -62,6 +61,18 @@ multiclass VPatUSLoadStoreSDNode<ValueType type,
             (store_instr reg_class:$rs2, RVVBaseAddr:$rs1, avl, sew)>;
 }
 
+multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m>
+{
+  defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#m.BX);
+  defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#m.BX);
+  // Load
+  def : Pat<(m.Mask (load RVVBaseAddr:$rs1)),
+            (load_instr RVVBaseAddr:$rs1, m.AVL, m.SEW)>;
+  // Store
+  def : Pat<(store m.Mask:$rs2, RVVBaseAddr:$rs1),
+            (store_instr VR:$rs2, RVVBaseAddr:$rs1, m.AVL, m.SEW)>;
+}
+
 class VPatBinarySDNode_VV<SDNode vop,
                           string instruction_name,
                           ValueType result_type,
@@ -352,8 +363,10 @@ let Predicates = [HasStdExtV] in {
 
 // 7.4. Vector Unit-Stride Instructions
 foreach vti = AllVectors in
-  defm "" : VPatUSLoadStoreSDNode<vti.Vector, vti.Mask, vti.SEW, vti.LMul,
+  defm "" : VPatUSLoadStoreSDNode<vti.Vector, vti.SEW, vti.LMul,
                                   vti.AVL, vti.RegClass>;
+foreach mti = AllMasks in
+  defm "" : VPatUSLoadStoreMaskSDNode<mti>;
 
 // 12.1. Vector Single-Width Integer Add and Subtract
 defm "" : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">;

diff  --git a/llvm/test/CodeGen/RISCV/rvv/load-mask.ll b/llvm/test/CodeGen/RISCV/rvv/load-mask.ll
new file mode 100644
index 000000000000..8a7277eba1ef
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/load-mask.ll
@@ -0,0 +1,89 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \
+; RUN:     -verify-machineinstrs | FileCheck %s
+; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \
+; RUN:     -verify-machineinstrs | FileCheck %s
+
+define void @test_load_mask_64(<vscale x 64 x i1>* %pa, <vscale x 64 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 64 x i1>, <vscale x 64 x i1>* %pa
+  store <vscale x 64 x i1> %a, <vscale x 64 x i1>* %pb
+  ret void
+}
+
+define void @test_load_mask_32(<vscale x 32 x i1>* %pa, <vscale x 32 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 32 x i1>, <vscale x 32 x i1>* %pa
+  store <vscale x 32 x i1> %a, <vscale x 32 x i1>* %pb
+  ret void
+}
+
+define void @test_load_mask_16(<vscale x 16 x i1>* %pa, <vscale x 16 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 16 x i1>, <vscale x 16 x i1>* %pa
+  store <vscale x 16 x i1> %a, <vscale x 16 x i1>* %pb
+  ret void
+}
+
+define void @test_load_mask_8(<vscale x 8 x i1>* %pa, <vscale x 8 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 8 x i1>, <vscale x 8 x i1>* %pa
+  store <vscale x 8 x i1> %a, <vscale x 8 x i1>* %pb
+  ret void
+}
+
+define void @test_load_mask_4(<vscale x 4 x i1>* %pa, <vscale x 4 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 4 x i1>, <vscale x 4 x i1>* %pa
+  store <vscale x 4 x i1> %a, <vscale x 4 x i1>* %pb
+  ret void
+}
+
+define void @test_load_mask_2(<vscale x 2 x i1>* %pa, <vscale x 2 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 2 x i1>, <vscale x 2 x i1>* %pa
+  store <vscale x 2 x i1> %a, <vscale x 2 x i1>* %pb
+  ret void
+}
+
+define void @test_load_mask_1(<vscale x 1 x i1>* %pa, <vscale x 1 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vle1.v v25, (a0)
+; CHECK-NEXT:    vse1.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 1 x i1>, <vscale x 1 x i1>* %pa
+  store <vscale x 1 x i1> %a, <vscale x 1 x i1>* %pb
+  ret void
+}