[PATCH] D95870: [RISCV] Support the scalable-vector fadd reduction intrinsic

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1731
+  SDValue ZeroIdx = DAG.getConstant(0, DL, Subtarget.getXLenVT());
+  SDValue ScalarInVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, M1VT,
+                                    DAG.getUNDEF(M1VT), ScalarVal, ZeroIdx);
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craig.topper wrote:
> I think ISD::SCALAR_TO_VECTOR is what we would more commonly use.
i guess we don't have a true scalar_to_vector instruction in RVV, i.e. an instruction that just moves a scalar register without being dependent on the previous vector register. So I think INSERT_VECTOR_ELT is ok.


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  https://reviews.llvm.org/D95870/new/

https://reviews.llvm.org/D95870