[PATCH] D95890: [RISCV] Alternate attempt to optimize sign-extended EXTRACT_VECTOR_ELT nodes.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added a reviewer: frasercrmck.
Herald added subscribers: vkmr, NickHung, ecnelises, evandro, luismarques, apazos, sameer.abuasal, pzheng, steven.zhang, s.egerton, Jim, benna, psnobl, jocewei, PkmX, jfb, the_o, brucehoult, MartinMosbeck, rogfer01, atanasyan, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson, sdardis.
craig.topper requested review of this revision.
Herald added a subscriber: MaskRay.
Herald added a project: LLVM.

This is an alternate version of D95741 <https://reviews.llvm.org/D95741> which defers the conversion
of extract_vector_elt to VMV_X_S until LegalDAG. This allows
it to be available to DAG combines for longer. To make this work
I've taught DAGCombiner to remove the SRA/SHL equivalent of
sext_inreg when the input to the pair is already sign extended.

If we decide to go this direction, I can split out the DAGCombiner
and Mips/atomic.ll change into a separate patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95890

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/Mips/atomic.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D95890.320875.patch
Type: text/x-patch
Size: 50058 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210202/558e17a1/attachment.bin>